- 15 May, 2018 40 commits
-
-
Harry Wentland authored
The below commit "drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2" introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it. Since DC is currently not equipped to handle this we need to fail such a commit, otherwise we might see a corrupted screen. This is based on Shirish's previous approach but avoids adding all planes to the new atomic state which leads to a full update in DC for any commit, and is not what we intend. Theoretically DM should be able to deal with states with fully populated planes, even for simple updates, such as cursor updates. This should still be addressed in the future. Signed-off-by:Harry Wentland <harry.wentland@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Cc: stable@vger.kernel.org Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Mikita Lipski authored
Merge amdgpu_dm_display_resume function into dm_resume, as it is not called anywhere else anymore. Initially the call was broken down into 2 functions for cursor corruption issue. Now the issue is not visible, hence the dm_resume will perform dm_display_resume in it. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
-
Mikita Lipski authored
Lock irq table when reading a work in queue, unlock to flush the work, lock again till all tasks are cleared Signed-off-by:
-
Emily Deng authored
After host os reset gpu reset, need to set flag in_gpu_reset to zero. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
-
Emily Deng authored
When put the IB test out of exclusive mode, and do sriov reset, the IB test will randomly fail. As out of exclusive mode it uses kiq to do read and write registers, but as it has world switch, the kiq read and write time will be random, sometimes it will beyond the MAX_KIQ_REG_WAIT and then the read or write register will fail, which will result the IB test fail. Signed-off-by:
-
Pixel Ding authored
The current sequence in scheduler thread is: 1. update last sched fence 2. job begin (adding to mirror list) 3. job finish (remove from mirror list) 4. back to 1 Since we update last sched prior to joining mirror list, the jobs in mirror list already pass the last sched fence. TDR just run the jobs in mirror list, so we should not update the last sched fences in TDR. Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
-
Eric Huang authored
Add the powertune table for VEGAM. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
-
Eric Huang authored
VEGAM specific changes for smu7: 1. add avfs control. 2. add a smc message defferent as smu7. 3. don't switch mc arb memory timing. 4. update LCAC_MC0/1_CNTL value. Signed-off-by:
-
Eric Huang authored
The smumgr handles communication between the driver and the SMU for power management. v2: fix typo (Alex) Signed-off-by:
-
Eric Huang authored
Add functionality to fetch gpio table from vbios. Signed-off-by:
-
Eric Huang authored
used for calculating memory clocks in powerplay. v2: handle endian swapping of atom data (Alex) Signed-off-by:
-
Eric Huang authored
Signed-off-by:
-
Eric Huang authored
Signed-off-by:
-
Harry Wentland authored
Some eDP displays use the extra link rate table to advertise link rate support. If they do that they don't need to provide link rate through the usual registers. Since we don't currently have support for the extra link rate table default to HBR2 for the display in this. Note that this is a HACK. Ultimately we need to teach DC to use the extra link rate table. Signed-off-by:
-
Alex Deucher authored
DC is preferred. Signed-off-by: -
Jerry (Fangzhi) Zuo authored
Add CHIP_VEGAM Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
-
Jerry (Fangzhi) Zuo authored
Implement device IDs for VEGAM Signed-off-by:
-
Leo Liu authored
Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
v2: use proper register rather than hardcoding. Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Directly loaded by VBIOS Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Leo Liu authored
Signed-off-by:
-
Mathieu Malaterre authored
AGP mode is unstable on PowerPC. Symptoms are generally of the form: [ 1228.795711] radeon 0000:00:10.0: ring 0 stalled for more than 10240msec Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
-
Rex Zhu authored
when bit14 in module parameter ppfeaturemask was set. od feature will be enabled on Vega10 except vbios not support. user can read od range by reading sysfs pp_od_clk_voltage, cat pp_od_clk_voltage OD_SCLK: 0: 852Mhz 800mV 1: 991Mhz 900mV 2: 1138Mhz 950mV 3: 1269Mhz 1000mV 4: 1348Mhz 1050mV 5: 1399Mhz 1100mV 6: 1440Mhz 1150mV 7: 1500Mhz 1200mV OD_MCLK: 0: 167Mhz 800mV 1: 500Mhz 800mV 2: 800Mhz 950mV 3: 945Mhz 1000mV OD_RANGE: SCLK: 852MHz 2200MHz MCLK: 167MHz 1500MHz VDDC: 800mV 1200mV and can configure the clock/voltage by writing pp_od_clk_voltage for example: echo "s 0 900 820">pp_od_clk_voltage to change the sclk/vddc to 900MHz and 820 mV in dpm level0. echo "r" to change the clk/voltage to default value. echo "c">pp_od_clk_voltage to commit the change v2: squash in warning fix (Alex) Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
-
