Commits · 3db2742554bb7cc077de478c2ebf9c1efdd317f5 · nexedi / linux

01 Apr, 2015 40 commits

MIPS: Use bool function return values of true/false not 1/0 · 3db27425

Joe Perches authored Mar 30, 2015

Use the normal return values for bool functions
Signed-off-by: Joe Perches <joe@perches.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9640/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3db27425

MIPS: Octeon: Fix to IP checksum offloading in Little Endian · 97b290b5

Paul Martin authored Mar 30, 2015

When hardware checksum generation is switched on the checksum
generation was only being signalled to the hardware correctly
in Big Endian mode.
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9634/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

97b290b5

MIPS: Octeon: Make octeon-md5 driver endian-agnostic · d2a948d2

Paul Martin authored Mar 30, 2015

The octeon crypto co-processor expects values to be big endian.
Wrap the data transfers with cpu_to_be64() and be64_to_cpu()
transformations.

This passes for all the MD5 test vectors in crypto/testmgr.h
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9631/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

d2a948d2

MIPS: Octeon: Set up ethernet hardware for little endian · 8a5cc923

Paul Martin authored Mar 30, 2015

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9635/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

8a5cc923

MIPS: Octeon: Reverse the order of register accesses to the FAU · f1e770cf

Paul Martin authored Mar 30, 2015

64 bit access is unaffected but for 32 bit access, swap high and
low words.  Similarly for 16 bit access, reverse the order of the
four possible words, and for 8 bit access reverse the order of byte
accesses.
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9630/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

f1e770cf

MIPS: Octeon: Set appropriate endianness in L2C registers · b0abf36f

Paul Martin authored Mar 30, 2015

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9629/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

b0abf36f

MIPS: Octeon: Turn hardware bitfields and structures inside out. · 11db04c8

Paul Martin authored Mar 30, 2015

Although the proper way to do this for bitfields would be to use
the macro that Ralf has provided, this is a little easier to
understand as a diff.
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9628/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

11db04c8

MIPS: IP32: ip32-platform is not a module. · 0a1cd2c5

Ralf Baechle authored Mar 30, 2015

So let's remove everything that only makes sense for kernel modules.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

0a1cd2c5

MIPS: Add R16000 detection · 30577391

Joshua Kinard authored Jan 21, 2015

This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those. Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9092/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

30577391

CLOCKSOURCE: mips-gic: Allow GIC clock to be specified in device-tree · 5b4e8453

Andrew Bresticker authored Feb 23, 2015

As an alternative to the "clock-frequency" property, allow the GIC
timer operating clock to be specified in the device-tree instead.
This is useful on systems which use common clock or where the GIC
is not fixed to a particular frequency and is instead, for example,
derived from the CPU clock.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9309/

5b4e8453

MIPS: csum_partial: Improve instruction parallelism. · 615eb603

Chen Jie authored Mar 27, 2015

Computing sum introduces true data dependency. This patch removes some
true data depdendencies, hence increases instruction level parallelism.

This patch brings up to 50% csum performance gain on Loongson 3a.

One example about how this patch works is in CSUM_BIGCHUNK1:
// ** original **    vs    ** patch applied **
    ADDC(sum, t0)           ADDC(t0, t1)
    ADDC(sum, t1)           ADDC(t2, t3)
    ADDC(sum, t2)           ADDC(sum, t0)
    ADDC(sum, t3)           ADDC(sum, t2)

In the original implementation, each ADDC(sum, ...) depends on the sum
value updated by previous ADDC(as source operand).

With this patch applied, the first two ADDC operations are independent,
hence can be executed simultaneously if possible.

Another example is in the "copy and sum calculating chunk":
// ** original **    vs    ** patch applied **
    STORE(t0, UNIT(0) ...   STORE(t0, UNIT(0) ...
    ADDC(sum, t0)           ADDC(t0, t1)
    STORE(t1, UNIT(1) ...   STORE(t1, UNIT(1) ...
    ADDC(sum, t1)           ADDC(sum, t0)
    STORE(t2, UNIT(2) ...   STORE(t2, UNIT(2) ...
    ADDC(sum, t2)           ADDC(t2, t3)
    STORE(t3, UNIT(3) ...   STORE(t3, UNIT(3) ...
    ADDC(sum, t3)           ADDC(sum, t2)

With this patch applied, ADDC and the **next next** ADDC are independent.
Signed-off-by: chenj <chenj@lemote.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9608/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

615eb603

MIPS: BCM47XX: Fix coding style to match kernel standards · d548ca6b

Rafał Miłecki authored Dec 10, 2014

[ralf@linux-mips.org: Fixed conflicts.]
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Paul Walmsley <paul@pwsan.com>
Patchwork: https://patchwork.linux-mips.org/patch/8665/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

d548ca6b

MIPS: OCTEON: add GPIO LED support for DSR-1000N · 05f5507f

Aaro Koskinen authored Mar 30, 2015

DSR-1000N board has two GPIO LEDs next to USB ports. Add support for them.

[ralf@linux-mips.org: Resolved conflict due to the moving of the DTS files
into vendor subdirectories.]
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9624/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

05f5507f

MIPS: Hibernate: Restructure files and functions · f8fd30eb

Huacai Chen authored Mar 29, 2015

This patch has no functional changes, it just to keep the assembler
code to a minimum. Files and functions naming is borrowed from X86.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9616/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

f8fd30eb

MIPS: Hibernate: flush TLB entries earlier · 2a21dc7c

Huacai Chen authored Mar 29, 2015

We found that TLB mismatch not only happens after kernel resume, but
also happens during snapshot restore. So move it to the beginning of
swsusp_arch_suspend().
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: <stable@vger.kernel.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9621/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2a21dc7c

MIPS: SEAD3: Nuke remaining I2C bits. · 4c9164b9

Ralf Baechle authored Mar 29, 2015

With no I2C driver available, keeping the platform device registration
makes no sense just as keeping the code to instantiage the I2C devices.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4c9164b9

MIPS: SEAD3: Nuke I2C driver that never was wired up in Makefile. · 968c94bc
Ralf Baechle authored Mar 29, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
968c94bc
MIPS: SEAD3: Use symbolic addresses from sead-addr.h in I2C driver. · e598e471
Ralf Baechle authored Mar 29, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
e598e471
MIPS: SEAD3: Use symbolic addresses from sead-addr.h in LED driver. · fbacc8df
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
fbacc8df
MIPS: SEAD3: New header file sead3-addr.h with hardware addresses. · be2d960e
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
be2d960e
MIPS: SEAD3: Get rid of DRVNAME from LED driver for readability. · 2c0916d4
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
2c0916d4
MIPS: SEAD3: Get rid of useless pr_debug calls in the LED driver. · 2ead2d73
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
2ead2d73
MIPS: SEAD3: Convert I2C driver to module_platform_driver. · 50a73f19
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
50a73f19
MIPS: SEAD3: Convert LED driver to module_platform_driver. · 4558e094
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
4558e094

MIPS: SEAD3: Collect LED platform device registration in a single file. · 01f7ab34

Ralf Baechle authored Oct 24, 2014

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Bryan Wu <cooloney@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: linux-leds@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8203/

01f7ab34

MIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC · 8a5f1efb

Florian Fainelli authored Mar 25, 2015

Since we are always sourcing arch/mips/bmips/Kconfig and there is no
dependency on BMIPS_GENERIC, we will offer building BMIPS-related DTBs
while this is not relevant for the other MIPS platforms.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jaedon.shin@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/9603/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

8a5f1efb

MIPS: BMIPS: Flush the readahead cache after DMA. · 554b7f56

Ralf Baechle authored Mar 27, 2015

BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC. To
avoid possible coherency problems, flush the RAC upon DMA completion.

Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

554b7f56

MIPS: DMA: Implement platform hook to perform post-DMA cache flushes. · 0acbfc66
Ralf Baechle authored Mar 27, 2015
```
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
```
0acbfc66

MIPS: ath25: Remove unused DMA helper functions. · 25307380

Ralf Baechle authored Mar 27, 2015

These got merged with the ath25 support after 4e7f7266 (MIPS: Remove
unnecessary platform dma helper functions) had already removed them for
all other platforms.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

25307380

MIPS: Loongson-3: remove deprecated IRQF_DISABLED · eec99f20

Michael Opdenacker authored Mar 26, 2015

This removes the use of the IRQF_DISABLED flag
from arch/mips/loongson/loongson-3/hpet.c

It's a NOOP since 2.6.35.
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Cc: chenhc@lemote.com
Cc: taohl@lemote.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9609/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

eec99f20

MIPS: BCM47xx: Move NVRAM header to the include/linux/. · 138173d4

Rafał Miłecki authored Dec 01, 2014

There are two reasons for having this header in the common place:
1) Simplifying drivers that read NVRAM entries. We will be able to
   safely call bcm47xx_nvram_* functions without #ifdef-s.
2) Getting NVRAM driver out of MIPS arch code. This is needed to support
   BCM5301X arch which also requires this NVRAM driver. Patch for that
   will follow once we get is reviewed.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-soc@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8619/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

138173d4

MIPS: Expand __swp_offset() to carry 40 significant bits for 64-bit kernel. · 5ae03b12

David Daney authored Feb 24, 2015

With CONFIG_MIGRATION, the PFN of the migrating pages is stored in
__swp_offset(), so we must have enough bits to store the largest
possible PFN.  OCTEON NUMA systems have 41 bits of physical address
space, so with 4K pages (12-bits), we need at least 29 bits to store
the PFN.

The current width of 24-bits is too narrow, so expand it all the way
out to 40-bits.  This leaves the low order 16 bits as zero which does
not interfere with any of the PTE bits.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9315/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

5ae03b12

MIPS: BCM47XX: Use strnchr to avoid reading out of the buffer · 80aaaa8b

Rafał Miłecki authored Dec 10, 2014

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8662/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

80aaaa8b

MIPS: BCM47XX: Use helpers for reading NVRAM content · 23d2bc42

Rafał Miłecki authored Dec 10, 2014

Also drop some unneeded memset-s.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8661/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

23d2bc42

MIPS: mark prom_free_prom_memory() everywhere with __init · aa816c1b

Aaro Koskinen authored Feb 26, 2015

On OCTEON the function is non-trivial and we can potentially even save
some memory.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9338/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

aa816c1b

MIPS: Provide fallback reboot/poweroff/halt implementations · f45e388f

Andrew Bresticker authored Mar 25, 2015

If a machine-specific hook is not implemented for restart, poweroff,
or halt, fall back to halting secondary CPUs, disabling interrupts,
and spinning.  In the case of restart, attempt to restart the system
via do_kernel_restart() (which will call any registered restart
handlers) before halting.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9600/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

f45e388f

MIPS: smp: Make stop_this_cpu() actually stop the CPU · ea925a72

Andrew Bresticker authored Mar 25, 2015

Since cpu_wait() enables interrupts upon return, CPUs which have
entered stop_this_cpu() may still end up handling interrupts.
This can lead to the softlockup detector firing on a panic or
restart/poweroff/halt.  Just disable interrupts and spin to ensure
nothing else runs on the CPU once it has entered stop_this_cpu().
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9601/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

ea925a72

MIPS: ath79: Increase max memory limit to 256MByte · c1bed31f

Helmut Schaa authored Dec 18, 2014

At least QCA955x can handle up to 256MBytes.
Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Cc: linux-mips@linux-mips.org
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Helmut Schaa <helmut.schaa@googlemail.com>
Patchwork: https://patchwork.linux-mips.org/patch/8738/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

c1bed31f

MIPS: Add FPU emulator counter for emulated delay slots. · 2707cd29

David Daney authored Dec 03, 2014

Delay slot emulation in the FPU emulator is the only kernel user of an
executable stack, it is also very slow.  Add a counter so we can see
how many of these emulations are done.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8634/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2707cd29

MIPS: Update arch/mips/include/asm/sgi/sgi.h · 7d168923

Joshua Kinard authored Dec 11, 2014

Update arch/mips/include/asm/sgi/sgi.h with some updated information on SGI
systems.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8666/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

7d168923