- 04 Dec, 2006 40 commits
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Benjamin Herrenschmidt authored
This is a small driver for the Xserve G5 CPU-meter blue LEDs on the front-panel. It might work on the Xserve G4 as well though that was not tested. It's pretty basic and could use some improvements if somebody cares doing them. :) Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Linas Vepstas authored
Per email discussion, it appears that rtas_stop_self() and pSeries_mach_cpu_die() should not be compiled if CONFIG_HOTPLUG_CPU is not defined. This patch adds #ifdefs around these bits of code. Signed-off-by:
Linas Vepstas <linas@austin.ibm.com> Signed-off-by:
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Zang Roy-r61911 authored
The following patch adds a tsi108/9 pci interrupt controller host. On mpc7448hpc2 board, pci_irq_fixup function is removed, which makes the pci_read_irq_line be the default pci irq fixup. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
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Kalle Pokki authored
The below hunk was missed from the recent patch, and now, there are somewhat inconsistent definitions: in cpm_uart.h: int __init cpm_uart_init_portdesc(void); in cpm_uart_cpm1.c: int __init cpm_uart_init_portdesc(void) { } in cpm_uart_cpm2.c: int cpm_uart_init_portdesc(void) { } Signed-off-by:Kalle Pokki <kalle.pokki@iki.fi> Signed-off-by:
Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by:
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Wojtek Kaniewski authored
Fix compilation without PCI support for Bubinga, CPCI405 and EP405. bios_fixup() for these boards uses functions available only with CONFIG_PCI, so linker fails. Signed-off-by:
Wojtek Kaniewski <wojtekka@toxygen.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
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nkalmala authored
PPC/booke reg MCSR value misquoted Signed-off-by:
nkalmala <nkalmala@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Hugh Dickins authored
Rewrite local_get_flags and local_irq_disable to use r13 explicitly, to avoid the risk that gcc will split get_paca()->soft_enabled into a sequence unsafe against preemption. Similar care in local_irq_restore. Signed-off-by:
Hugh Dickins <hugh@veritas.com> Signed-off-by:
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Stephen Rothwell authored
Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
On error, make sure that we undo all necessary operations. This also gets rid of a must_check warning. Signed-off-by:
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Benjamin Herrenschmidt authored
The recent IO accessor changes broke IDE on arch/ppc due to the IDE stream IO macros using the new reads/writes{b,w,l} accessors that are only defined for arch/powerpc. This adds them to arch/ppc. Signed-off-by: -
Benjamin Herrenschmidt authored
The new IO accessor code allows to stick a token in the top bit of MMIO addresses which gets masked out during actual accesses. However, the __raw_* accessors forgot to mask it out. This fixes it. Signed-off-by:
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Benjamin Herrenschmidt authored
powerpc: Merge 32 and 64 bits asm-powerpc/io.h The rework on io.h done for the new hookable accessors made it easier, so I just finished the work and merged 32 and 64 bits io.h for arch/powerpc. arch/ppc still uses the old version in asm-ppc, there is just too much gunk in there that I really can't be bothered trying to cleanup. Signed-off-by:
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Benjamin Herrenschmidt authored
In order to suppose platforms with devices above 4Gb on 32 bits platforms with a >32 bits physical address space, we used to have a special ioremap64 along with a fixup routine fixup_bigphys_addr. This shouldn't be necessary anymore as struct resource now supports 64 bits addresses even on 32 bits archs. This patch enables that option when CONFIG_PHYS_64BIT is set and removes ioremap64 and fixup_bigphys_addr. This is a preliminary work for the upcoming merge of 32 and 64 bits io.h Signed-off-by:
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Jeremy Kerr authored
This patch adds full cell iommu support (and iommu disabled mode). It implements mapping/unmapping of iommu pages on demand using the standard powerpc iommu framework. It also supports running with iommu disabled for machines with less than 2GB of memory. (The default is off in that case, though it can be forced on with the kernel command line option iommu=force). Signed-off-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
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Benjamin Herrenschmidt authored
Now that the direct DMA ops supports an offset, we use that instead of defining our own. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch makes dma_alloc_coherent() use node local allocation when using the direct DMA ops. The node is obtained from the new device extension. If no such extension is present, the current node is used. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch adds an optional global offset that can be added to DMA addresses when using the direct DMA operations. That brings it a step closer to the 32 bits direct DMA operations, and makes it useable on Cell when the MMU is disabled and we are using a spider southbridge. Signed-off-by:
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Benjamin Herrenschmidt authored
We use the powerpc specific low level MMIO accessor variants instead of readl() or readl_be() because we know spidernet is not a real PCI device and we can thus avoid the performance hit caused by the PCI workarounds. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch implements a workaround for a Spider PCI host bridge bug where it doesn't enforce some of the PCI ordering rules unless some manual manipulation of a special register is done. In order to be fully compliant with the PCI spec, I do this on every MMIO read operation. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO and PIO) and provides a generic way for other platforms to do so (we have need to do that for various other platforms). While reworking the IO ops, I ended up doing some spring cleaning in io.h and eeh.h which I might want to split into 2 or 3 patches (among others, eeh.h had a lot of useless stuff in it). A side effect is that EEH for PIO should work now (it used to pass IO ports down to the eeh address check functions which is bogus). Also, new are MMIO "repeat" ops, which other archs like ARM already had, and that we have too now: readsb, readsw, readsl, writesb, writesw, writesl. In the long run, I might also make EEH use the hooks instead of wrapping at the toplevel, which would make things even cleaner and relegate EEH completely in platforms/iseries, but we have to measure the performance impact there (though it's really only on MMIO reads) Since I also need to hook on ioremap, I shuffled the functions a bit there. I introduced ioremap_flags() to use by drivers who want to pass explicit flags to ioremap (and it can be hooked). The old __ioremap() is still there as a low level and cannot be hooked, thus drivers who use it should migrate unless they know they want the low level version. The patch "arch provides generic iomap missing accessors" (should be number 4 in this series) is a pre-requisite to provide full iomap API support with this patch. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch makes the Cell DMA code work on both the Spider and the Axon south bridges by turning cell_dma_valid into a variable instead of a constant. This is a temporary patch until we have full iommu support. Signed-off-by:
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Benjamin Herrenschmidt authored
When enabled in Kconfig, it will pick up any of_platform_device matching it's match list (currently type "pci", "pcix", "pcie", or "ht" and setup a PHB for it. Platform must provide a ppc_md.pci_setup_phb() for it to work (for doing the necessary initialisations specific to a given PHB like setting up the config space ops). It's currently only available on 64 bits as the 32 bits PCI code can't quite cope with it in it's current form. I will fix that later. Signed-off-by:
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Benjamin Herrenschmidt authored
Add a "parent" struct device to our PCI host bridge data structure so that PCI can be rooted off another device in sysfs. Note that arch/ppc doesn't use it, only arch/powerpc, though it's available for both 32 and 64 bits. Signed-off-by:
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Benjamin Herrenschmidt authored
The BUID is the first entry of a PCI host bridge "reg" property. Now that PCI busses can be anywhere in the device-tree, we need to fully translate the value there to a CPU physical address before we can use it with RTAS. Signed-off-by:
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Benjamin Herrenschmidt authored
When parsing the OF "ranges" properties of PCI host busses to determine the mapping of a PCI bus, we need to translate the "parent" address using the prom_parse.c routines in order to obtain a CPU physical address. This wasn't necessary while PCI busses were always at the root of the device-tree but this is no longer the case on Cell where they can be anywhere in the tree. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch adds a bus device notifier to the of_platform bus type on cell to setup the DMA operations for of_platform_devices. We currently use the PCI operations as Cell use a special version of them that happens to be suitable for our needs. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch completely refactors DMA operations for 64 bits powerpc. 32 bits is untouched for now. We use the new dev_archdata structure to add the dma operations pointer and associated data to struct device. While at it, we also add the OF node pointer and numa node. In the future, we might want to look into merging that with pci_dn as well. The old vio, pci-iommu and pci-direct DMA ops are gone. They are now replaced by a set of generic iommu and direct DMA ops (non PCI specific) that can be used by bus types. The toplevel implementation is now inline. Signed-off-by:
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Benjamin Herrenschmidt authored
Remove the now unused "liobn" field in ibmveth which also avoids having insider knowledge of the iommu table in that driver. Signed-off-by:
Santiago Leon <santil@us.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
Hook up of_platform_bus_probe with the cell platform in order to publish the non-PCI devices in the device-tree of cell blades as of_platform_device(s) Signed-off-by:
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Benjamin Herrenschmidt authored
This patch first splits of_device.c and of_platform.c, the later containing the bits relative to of_platform_device's. On the "breaks" side of things, drivers uisng of_platform_device(s) need to include asm/of_platform.h now and of_(un)register_driver is now of_(un)register_platform_driver. In addition to a few utility functions to locate of_platform_device(s), the main new addition is of_platform_bus_probe() which allows the platform code to trigger an automatic creation of of_platform_devices for a whole tree of devices. The function acts based on the type of the various "parent" devices encountered from a provided root, using either a default known list of bus types that can be "probed" or a passed-in list. It will only register devices on busses matching that list, which mean that typically, it will not register PCI devices, as expected (since they will be picked up by the PCI layer). This will be used by Cell platforms using 4xx-type IOs in the Axon bridge and can be used by any embedded-type device as well. Signed-off-by:
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Benjamin Herrenschmidt authored
Add support for southbridges using the MPIC interrupt controller to the native cell platforms. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch applies on top of the MPIC DCR support. It makes the MPIC driver capable of a lot more auto-configuration based on the device-tree, for example, it can retreive it's own physical address if not passed as an argument, find out if it's DCR or MMIO mapped, and set the BIG_ENDIAN flag automatically in the presence of a "big-endian" property in the device-tree node. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch implements support for DCR based MPIC implementations. Such implementations have the MPIC_USES_DCR flag set and don't use the phys_addr argument of mpic_alloc (they require a valid dcr mapping in the device node) This version of the patch can use a little bif of cleanup still (I can probably consolidate rb->dbase/doff, at least once I'm sure on how the hardware is actually supposed to work vs. possible simulator issues) and it should be possible to build a DCR-only version of the driver. I need to cleanup a bit the CONFIG_* handling for that and probably introduce CONFIG_MPIC_MMIO and CONFIG_MPIC_DCR. Signed-off-by:
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Benjamin Herrenschmidt authored
This patch makes the EMAC driver use the new DCR access methods. It doesn't yet uses dcr_map() and thus still only work with real DCRs. This will be fixed in a later patch Signed-off-by:
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Benjamin Herrenschmidt authored
This patch adds new dcr_map/dcr_read/dcr_write accessors for DCRs that can be used by drivers to transparently address either native DCRs or memory mapped DCRs. The implementation for memory mapped DCRs is done after the binding being currently worked on for SLOF and the Axon chipset. This patch enables it for the cell native platform Signed-off-by:
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Benjamin Herrenschmidt authored
These were inherited from ARCH=ppc, but are not needed since parsing of interrupts should be done via the of_* functions (who can do swizzling). If we ever need to do non-standard swizzling on bridges without a device-node, then we might add back a slightly different version of ppc_md.pci_swizzle but for now, that is not the case. I removed the couple of calls for these in 83xx. If that breaks something, then there is a problem with the device-tree on these. Signed-off-by:
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