- 07 Jun, 2017 4 commits
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Alex Deucher authored
Same function was duplicated in all gfx IP files. Reviewed-by:
Alex Xie <AlexBin.Xie@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Fixes hangs on single MEC asics. Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of each pipe v2) Reviewed-by:
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Alex Deucher authored
The same function was duplicated in all the gfx IPs. Use a single implementation for all. v2: use static inline (Alex Xie) Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Alex Deucher authored
Always use the max for the family rather than the per sku limits. This makes sure the mask is always the max size to avoid reporting the wrong number of CUs. Reviewed-by:
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- 06 Jun, 2017 28 commits
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Alex Deucher authored
This was missing for gfx6. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Alex Deucher authored
Instead of taking the first pipe and giving the rest to kfd, take the first 2 queues of each pipe. Effectively, amdgpu and amdkfd own the same number of queues. But because the queues are spread over multiple pipes the hardware will be able to better handle concurrent compute workloads. amdgpu goes from 1 pipe to 4 pipes, i.e. from 1 compute threads to 4 amdkfd goes from 3 pipe to 4 pipes, i.e. from 3 compute threads to 4 gfx9 was missed when this patch set was rebased to include gfx9. Acked-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Alex Deucher authored
Pipes provide better concurrency than queues, therefore we want to make sure that apps use queues from different pipes whenever possible. Optimize for the trivial case where an app will consume rings in order, therefore we don't want adjacent rings to belong to the same pipe. gfx9 was missed when these patches were rebased. Reviewed-by:
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Hawking Zhang authored
vddc_dep_on_dal_pwrl is allocated and initialized in cz_hwmgr_backend_init Thus free the memory in cz_hwmgr_backend_fini Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
vddc_dep_on_dal_pwrl and vq_budgeting_table are allocated and initialized in rv_hwmgr_backend_init. Thus free the memory in rv_hwmgr_backend_fini Signed-off-by:
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Eric Huang authored
For overclocking sclk and mclk. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Rex Zhu authored
As the min clk may be large than boot level can support. in this case, just ignore the min clk. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
Something writes over the first 8 MB so reserve this on vega10 until we root cause it. Signed-off-by:
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Huang Rui authored
User is able to follow the ip block number to write the ip_block_mask for selecting the one which user would like to enable. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
This patch moves invalidation into gart enable function from hw_init. Because we would like align the sequence calling between init and resume. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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- 01 Jun, 2017 7 commits
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Leo Liu authored
We are using PSP to resume firmware after suspend, and it is resumed at where it got suspended, so we'd better save the the context. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
To simplify vce bo create Signed-off-by:
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Leo Liu authored
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Alex Xie authored
In review, Christian would like to keep the logic inside amdgpu_vm.c with a cost of slightly slower. The loop is still optimized out with this patch. v2: remove the if statement. Now it is not slower. Signed-off-by:
Christian König <christian.koeng@amd.com> Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
Use the vbios to look up the default frequencies for socclk and dcefclk. Signed-off-by:
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- 31 May, 2017 1 commit
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Andres Rodriguez authored
Spreading the load across multiple SDMA engines can increase memory transfer performance. Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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