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  1. 26 Mar, 2018 5 commits
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  13. 02 Mar, 2018 9 commits
    • Manivannan Sadhasivam's avatar
      dt-bindings: pinctrl: Add bindings for Actions S900 SoC · 2ba08d75
      Manivannan Sadhasivam authored 
      Add pinctrl bindings for Actions Semi S900 SoC
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      2ba08d75
    • Linus Walleij's avatar
      Merge tag 'sh-pfc-for-v4.17-tag1' of... · e024484a
      Linus Walleij authored 
      Merge tag 'sh-pfc-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.17

  - Add DU and VIN pin groups on R-Car D3,
  - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W,
  - Add support for the new R-Car M3-N SoC,
  - Small fixes and cleanups.
      e024484a
    • Richard Fitzgerald's avatar
      pinctrl: core: Add missing EXPORT on pinctrl_register_mappings · 8b1b2dc7
      Richard Fitzgerald authored 
      Systems that don't have devicetree need pinctrl_register_mappings.
It should be EXPORT_SYMBOL_GPL so that it can be called from
pinctrl drivers built as modules.
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      8b1b2dc7
    • Martin Blumenstingl's avatar
      pinctrl: meson: meson8b: fix requesting GPIOs greater than GPIOZ_3 · 55af415b
      Martin Blumenstingl authored 
      Meson8b is a cost reduced variant of the Meson8 SoC. It's package size
is smaller than Meson8.
Unfortunately there are a few key differences which cannot be seen
without close inspection of the code and the public S805 datasheet:
- the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and
  GPIOX_15 GPIOs
- the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and
  GPIOY_16 GPIOs
- the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24,
  GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29
- the GPIOZ bank is missing completely
- there is a new GPIO bank called "DIF"

This means that Meson8b only has 83 actual GPIO lines. Without any holes
there would be 130 GPIO lines in total (120 are inherited from Meson8
plus 10 new from the DIF bank).

GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly
the number of actual GPIO lines on Meson8b and also the value of
meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6
(which used ID 100 prior to this patch, "base of the GPIO controller was
382) as an example:
$ echo 482 > /sys/class/gpio/export
export_store: invalid GPIO 482

This removes all non-existing pins from to dt-bindings header file
(include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a
consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for
example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this
patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get
compile-time (instead of runtime) errors if Meson8b .dts uses a pin that
only exists on Meson8.

Additionally the pinctrl-meson8b driver has to be updated to handle this
new GPIO numbering. By default a struct meson_bank only handles GPIO
banks where the pins are numbered consecutively because it calculates
the bit offsets based on the GPIO IDs.
This is solved by  taking the original BANK() definition and splitting it
into consecutive subsets (X0..11 and X16..21). The bit offsets for each
new bank includes the skipped GPIOs (the definition of the "X0..11" bank
is identical to the old "X" bank apart from the "last IRQ" field, the
definition of the new, split "X16..21" bank takes the original "X" bank
and adds 16 - the start of the new split bank - to the "first IRQ",
pullen bit, pull bit, dir bit, out bit and in bit).

Commit 984cffde ("pinctrl: Fix gpio/pin mapping for Meson8b")
fixed the same issue by setting "ngpio" (of the gpio_chip) to 130.
Unfortunately this broke in db80f0e1 ("pinctrl: meson: get rid of
unneeded domain structures").
The solution from this patch was considered to be better than the
previous attempt at fixing this because it provides compile-time error
checking for the GPIOs that exist on Meson8 but don't exist on Meson8b.

The following pins were tested on an Odroid-C1 using the sysfs GPIO
interface checking that their value (high or low) could be read:
- GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6,
  GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19,
  GPIOX_20, GPIOX_21
- GPIOY_3, GPIOY_7, GPIOY_8
(some of these had to be pulled up because they were low by default,
others were high by default so these had to be pulled down)
Reported-by: default avatarLinus Lüssing <linus.luessing@c0d3.blue>
Suggested-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      55af415b
    • Richard Fitzgerald's avatar
      pinctrl: devicetree: Fix dt_to_map_one_config handling of hogs · b89405b6
      Richard Fitzgerald authored 
      When dt_to_map_one_config() is called with a pinctrl_dev passed
in, it should only be using this if the node being looked up
is a hog. The code was always using the passed pinctrl_dev
without checking whether the dt node referred to it.

A pin controller can have pinctrl-n dependencies on other pin
controllers in these cases:

- the pin controller hardware is external, for example I2C, so
  needs other pin controller(s) to be setup to communicate with
  the hardware device.

- it is a child of a composite MFD so its of_node is shared with
  the parent MFD and other children of that MFD. Any part of that
  MFD could have dependencies on other pin controllers.

Because of this, dt_to_map_one_config() can't assume that if it
has a pinctrl_dev passed in then the node it looks up must be
a hog. It could be a reference to some other pin controller.
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      b89405b6
    • Sean Wang's avatar
      dt-bindings: pinctrl: mediatek: add bindings for I2C2 and SPI2 on MT7623 · 536836d3
      Sean Wang authored 
      Add missing pinctrl binding about I2C2 and SPI2 which would be used in
devicetree related files.
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      536836d3
    • Sean Wang's avatar
      dt-bindings: pinctrl: mediatek: use - instead of _ in examples · fc471710
      Sean Wang authored 
      It should be good that no use "_" is in examples. Consequently,
those nodes in certain files which have an inappropriate name containing
"_" are all being replaced with "-".
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      fc471710
    • Radoslaw Pietrzyk's avatar
      pinctrl: stm32: Optimizes and enhances stm32gpio irqchip · 430a2a59
      Radoslaw Pietrzyk authored 
      - removes unneeded irq_chip.irq_eoi callback
- adds irq_chip.irq_set_wake callback for possible
  in the future GPIO wakeup
- adds irq_chip.irq_ack callback
Signed-off-by: default avatarRadoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Reviewed-by: default avatarLudovic Barre <ludovic.barre@st.com>
Tested-by: default avatarLudovic Barre <ludovic.barre@st.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      430a2a59
    • Niklas Cassel's avatar
      pinctrl: artpec6: dt: add smaller groups for uarts · 928af224
      Niklas Cassel authored 
      Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.

This allows us to be more precise in which pins we're
actually using.

Unfortunately the existing naming scheme leaves things
to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS,
yet uart0grp0 means all pins.
Since the exising suffixes have different meaning for
different uarts, and the fact that we cannot change
the name of existing groups, makes it hard to use a
descriptive name for the newly added groups.
Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      928af224
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