- 08 Jun, 2016 17 commits
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Mika Kuoppala authored
This workaround is for fbc working with rc6 on skylake. Bspec states that setting this bit needs to be coordinated with uncore but offers no further details. v2: rebase References: HSD#4712857 Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-18-git-send-email-mika.kuoppala@intel.com
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Mika Kuoppala authored
Make sure that we never enable skip caching on gen9 by accident. References: HSD#2134698 Signed-off-by:
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Mika Kuoppala authored
Add this workaround for both bxt and kbl up to until rev B0. References: HSD#2136703 Signed-off-by:
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Mika Kuoppala authored
Bspec states that we need to turn off dynamic credit sharing on kbl revid a0 and b0. This happens by writing bit 28 on 0x4ab8. References: HSD#2225601, HSD#2226938, HSD#2225763 Signed-off-by:
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Mika Kuoppala authored
According to bspec we need to disable gam unit clock gating on on kbl revids A0 and B0. References: HSD#2226858, HSD#1944358 Signed-off-by:
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Mika Kuoppala authored
The bspec states that these must be set in CONFIG0 for all gen9. v2: rebase v3: fix spacing (Matthew) References: HSD#2134995 Signed-off-by:
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Mika Kuoppala authored
Extend the scope of this workaround, already used in skl, to also take effect in kbl. v2: Fix KBL_REVID_E0 (Matthew) References: HSD#2132677 Cc: Matthew Auld <matthew.william.auld@gmail.com> Signed-off-by:
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Mika Kuoppala authored
According to bspec this workaround helps to reduce lag and improve performance on edp. Documentation suggests this for bdw and all gen9. However evidence shows that this register is missing on gen9 and causing unclaimed mmio access if we access it. So apply to bdw only where the reg exists and can hold its value. v2: drop skl References: HSD#2134579 Signed-off-by:
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Mika Kuoppala authored
Add this workaround until upto kbl revid B0. References: HSD#1802092 Signed-off-by:
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Mika Kuoppala authored
Add this workaround for kbl revid A0 only. v2: rebase v3: carve out a non related workaround (Chris) References: HSD#1911714 Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Mika Kuoppala authored
We need this crucial workaround from skl also to all kbl revisions. Lack of it was causing system hangs on skl enabling so this is a must have. v2: Don't add revid checks to gen9 init workarounds (Arun) References: HSD#2126660 Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by:
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Mika Kuoppala authored
Past evidence with system hangs and hsds tie WaForceEnableNonCoherent and WaDisableHDCInvalidation to WaForceContextSaveRestoreNonCoherent. Documentation states that WaForceContextSaveRestoreNonCoherent would not be needed on skl past E0 but evidence proved otherwise. See commit <510650e8> ("drm/i915/skl: Fix spurious gpu hang with gt3/gt4 revs"). In this scope consider kbl to be skl with a bigger revision than E0 so play it safe and bind these two workarounds to the WaForceContextSaveRestoreNonCoherent, and apply to all gen9. v2: fix comment (Matthew) References: HSD#2134449, HSD#2131413 Signed-off-by:
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Mika Kuoppala authored
The revision id range for this workaround has changed. So apply it to all revids on all gen9. References: HSD#2134449 Signed-off-by:
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Mika Kuoppala authored
We need this for kbl a0 boards. Note that this should be also for bxt A0 but we omit that on purpose as bxt A0's are out of fashion already. References: HSD#1912158, HSD#4393097 Signed-off-by:
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Mika Kuoppala authored
Add REVID macro for kbl to limit wa applicability to particular revision range. Signed-off-by:
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Mika Kuoppala authored
Kabylake is part of gen9 family so init the generic gen9 workarounds for it. v2: rebase Signed-off-by:
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Mika Kuoppala authored
We need to disable clock gating in this unit to work around hardware issue causing possible corruption/hang. v2: name the bit (Ville) v3: leave the fix enabled for 2227050 and set correct bit (Matthew) References: HSD#2227156, HSD#2227050 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by:
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- 07 Jun, 2016 5 commits
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David Weinehall authored
The atomic version of intel_pre_plane_update did not check for HAS_GMCH_DISPLAY before calling intel_set_memory_cxsr(). While this doesn't cause any issues on its own (it will return without doing anything if the hardware doesn't have the required feature), the drm_wait_one_vblank() that is needed if memory self-refresh is disabled introduces an unnecessary delay in the suspend path. In cases where i915 is on the critical path it means that we slow down suspend by 16.8ms on platforms that don't need to disable memory self-refresh. Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463662236-18192-1-git-send-email-david.weinehall@linux.intel.comReviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ville Syrjälä authored
Apparently some CHV boards failed to hook up the port presence straps for HDMI ports as well (earlier we assumed this problem only affected eDP ports). So let's check the VBT in addition to the strap, and if either one claims that the port is present go ahead and register the relevant connector. While at it, change port D to register DP before HDMI as we do for ports B and C since commit 457c52d8 ("drm/i915: Only ignore eDP ports that are connected") Also print a debug message when we register a HDMI connector to aid in diagnosing missing/incorrect ports. We already had such a print for DP/eDP. v2: Improve the comment in the code a bit, note the port D change in the commit message Cc: Radoslav Duda <radosd@radosd.com> Tested-by:
Radoslav Duda <radosd@radosd.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96321Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Dave Gordon authored
The recent patch . fce91f22 drm/i915/guc: add enable_guc_loading parameter enabled GuC loading and submission by default, but as issues were found with warnings being issued during suspend-resume cycles, GuC loading was disabled by default, by patch . 2335986d drm/i915/guc: Disable automatic GuC firmware loading Those warnings have been resolved, so this patch re-enables GuC loading and submission by default. Signed-off-by:
Dave Gordon <david.s.gordon@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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Dave Gordon authored
When resetting and reloading the GuC, the GuC submission management code also needs to destroy and recreate the GuC client(s). Currently this is done by a separate call from the GuC loader, but really, it's just an internal detail of the submission code. So here we remove the call from the loader (which is too late, really, because the GuC has already been reloaded at this point) and put it into guc_submission_init() instead. This means that any preexisting client is destroyed *before* the GuC (re)load and then recreated after, iff the firmware was successfully loaded. If the GuC reload fails, we don't recreate the client, so fallback to execlists mode (if active) won't leak the client object (previously, the now-unusable client would have been left allocated, and leaked if the driver were unloaded). Signed-off-by:
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Dave Gordon authored
The last stage of the GuC loader also sanitises the GuC submission settings, so should be called unconditionally (even on platforms without a GuC) to ensure consistent settings; in particular, this prevents any attempt to use GuC submission on GuCless platforms! Also fix error path handling and clarify DRM_INFO fallback message. Signed-off-by:
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- 06 Jun, 2016 3 commits
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arun.siluvery@linux.intel.com authored
Kernel only need to add a register to HW whitelist, required for a preemption related issue. Reference: HSD#2131039 Reviewed-by:
Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by:
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Tvrtko Ursulin authored
Just a bunch of stale kerneldocs generating warnings when building the docs. Mostly function parameters so not very useful but still. v2: Tidy. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1464958937-23344-1-git-send-email-tvrtko.ursulin@linux.intel.com
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Jani Nikula authored
Fix the failure mode where the display appears split, or shifted about 2/3 of the screen, and the color components are cycled. Turns out we were missing the crucial BXT_DEFEATURE_DPI_FIFO_CTR bit in the EOT_DISABLE register. Per bspec, with the bit set, the "mipi_dpf_vblank_start" signal is asserted only when the complete frame is transferred in the DPHY line and also the DPI FIFO is flushed out at the end of each frame. The problem was mitigated by keeping the panel fitter enabled, but that only limited the issue to a shift of about 0..10 pixels. With the fix here, the panel fitter workaround does not seem to be needed at all. While at it, set BXT_DPHY_DEFEATURE_EN in EOT_DISABLE register which is also needed per the BXT DSI mode set sequence. Issue: VIZ-7610 Cc: Mika Kahola <mika.kahola@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1464965825-31035-1-git-send-email-jani.nikula@intel.com
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- 05 Jun, 2016 1 commit
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Daniel Vetter authored
Signed-off-by:
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- 02 Jun, 2016 3 commits
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Ville Syrjälä authored
The VBT has these mysterious H/V image sizes as part of the display timings. Looking at some dumps those appear to be the physical dimensions in mm. Which makes sense since the timing descriptor matches the format used by EDID detailed timing descriptor, which defines these as "H/V Addressable Video Image Size in mm". So let's use that information from the panel fixed mode to get the physical dimensions for LVDS/eDP/DSI displays. And with that we can fill out the display_info so that userspace can get at it via GetConnector. v2: Use (hi<<8)|lo instead of broken (hi<<4)+lo Handle LVDS and eDP too Cc: Stephen Just <stephenjust@gmail.com> Tested-by:Stephen Just <stephenjust@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96255Signed-off-by:
Mika Kahola <mika.kahola@intel.com>
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Chris Wilson authored
My old 845g complains that the child_device_size inside its VBT, version 110, is incorrect. Let's fiddle with the version matching such that it works with this VBT (i.e. treat BIOS v110 as having the same size as v108). Fixes [drm:intel_bios_init] *ERROR* Unexpected child device config size 27 (expected 33 for VBT version 110) Whether this is correct, no one knows - but it works for this particular machine. Signed-off-by:
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Daniel Vetter authored
Git got absolutely destroyed with all our cherry-picking from drm-intel-next-queued to various branches. It ended up inserting intel_crtc_page_flip 2x even in intel_display.c. Backmerge to get back to sanity. Signed-off-by:Daniel Vetter <daniel.vetter@intel.com>
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- 01 Jun, 2016 8 commits
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
drm-intel-next-2016-05-22: - cmd-parser support for direct reg->reg loads (Ken Graunke) - better handle DP++ smart dongles (Ville) - bxt guc fw loading support (Nick Hoathe) - remove a bunch of struct typedefs from dpll code (Ander) - tons of small work all over to avoid casting between drm_device and the i915 dev struct (Tvrtko&Chris) - untangle request retiring from other operations, also fixes reset stat corner cases (Chris) - skl atomic watermark support from Matt Roper, yay! - various wm handling bugfixes from Ville - big pile of cdclck rework for bxt/skl (Ville) - CABC (Content Adaptive Brigthness Control) for dsi panels (Jani&Deepak M) - nonblocking atomic commits for plane-only updates (Maarten Lankhorst) - bunch of PSR fixes&improvements - untangle our map/pin/sg_iter code a bit (Dave Gordon) drm-intel-next-2016-05-08: - refactor stolen quirks to share code between early quirks and i915 (Joonas) - refactor gem BO/vma funcstion (Tvrtko&Dave) - backlight over DPCD support (Yetunde Abedisi) - more dsi panel sequence support (Jani) - lots of refactoring around handling iomaps, vma, ring access and related topics culmulating in removing the duplicated request tracking in the execlist code (Chris & Tvrtko) includes a small patch for core iomapping code - hw state readout for bxt dsi (Ramalingam C) - cdclk cleanups (Ville) - dedupe chv pll code a bit (Ander) - enable semaphores on gen8+ for legacy submission, to be able to have a direct comparison against execlist on the same platform (Chris) Not meant to be used for anything else but performance tuning - lvds border bit hw state checker fix (Jani) - rpm vs. shrinker/oom-notifier fixes (Praveen Paneri) - l3 tuning (Imre) - revert mst dp audio, it's totally non-functional and crash-y (Lyude) - first official dmc for kbl (Rodrigo) - and tons of small things all over as usual * 'drm-intel-next' of git://anongit.freedesktop.org/drm-intel: (194 commits) drm/i915: Revert async unpin and nonblocking atomic commit drm/i915: Update DRIVER_DATE to 20160522 drm/i915: Inline sg_next() for the optimised SGL iterator drm/i915: Introduce & use new lightweight SGL iterators drm/i915: optimise i915_gem_object_map() for small objects drm/i915: refactor i915_gem_object_pin_map() drm/i915/psr: Implement PSR2 w/a for gen9 drm/i915/psr: Use ->get_aux_send_ctl functions drm/i915/psr: Order DP aux transactions correctly drm/i915/psr: Make idle_frames sensible again drm/i915/psr: Try to program link training times correctly drm/i915/userptr: Convert to drm_i915_private drm/i915: Allow nonblocking update of pageflips. drm/i915: Check for unpin correctness. Reapply "drm/i915: Avoid stalling on pending flips for legacy cursor updates" drm/i915: Make unpin async. drm/i915: Prepare connectors for nonblocking checks. drm/i915: Pass atomic states to fbc update functions. drm/i915: Remove reset_counter from intel_crtc. drm/i915: Remove queue_flip pointer. ...
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
Frist -misc pull for 4.8, with pretty much just random all over plus a few more lockless gem BO patches acked/reviewed by driver maintainers. I'm starting a bit earlier this time around because there's a few invasive patch series to land (nonblocking atomic prep work, fence prep work, rst/sphinx kerneldoc finally happening) and I need a baseline with all the branches merged. * tag 'topic/drm-misc-2016-06-01' of git://anongit.freedesktop.org/drm-intel: (21 commits) drm/vc4: Use lockless gem BO free callback drm/vc4: Use drm_gem_object_unreference_unlocked drm: Initialize a linear gamma table by default drm/vgem: Use lockless gem BO free callback drm/qxl: Don't set a gamma table size drm/msm: Nuke dummy gamma_set/get functions drm/cirrus: Drop redundnant gamma size check drm/fb-helper: Remove dead code in setcolreg drm/mediatek: Use lockless gem BO free callback drm/hisilicon: Use lockless gem BO free callback drm/hlcd: Use lockless gem BO free callback vga_switcheroo: Support deferred probing of audio clients vga_switcheroo: Add helper for deferred probing virtio-gpu: fix output lookup drm/doc: Unify KMS Locking docs drm/atomic-helper: Do not call ->mode_fixup for CRTC which will be disabled Fix annoyingly awkward typo in drm_edid_load.c drm/doc: Drop vblank_disable_allow wording drm: use seqlock for vblank time/count drm/mm: avoid possible null pointer dereference ...
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Kumar, Mahesh authored
if downscaling is enabled plane data rate increases according to scaling amount. take scaling amount under consideration while calculating plane data rate v2: Address Matt's comments, where data rate was overridden because of missing else. v3 (by Matt): - Add braces to 'else' branch to match kernel coding style - Adjust final calculation now that skl_plane_downscale_amount() returns 16.16 fixed point value instead of a decimal fixed point v4 (by Matt): - Avoid integer overflow by making sure final multiplication is treated as 64-bit. Cc: matthew.d.roper@intel.com Signed-off-by:
Kumar, Mahesh <mahesh1.kumar@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Kumar, Mahesh authored
Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel according to formula adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w] if 90/270 rotation use rotated width & height v2: use intel_plane_state->visible instead of (fb == NULL) as per Matt's comment. v3 (by Matt): - Keep downscale amount in 16.16 fixed point rather than converting to decimal fixed point. - Store adjusted plane pixel rate in plane state instead of the plane parameters structure that we no longer use. v4 (by Matt): - Significant rebasing onto latest atomic watermark work - Don't bother storing plane pixel rate in state; just calculate it right before the calls that make use of it. - Fix downscale calculations to actually use width values when computing downscale_w rather than copy/pasted height values. Cc: matthew.d.roper@intel.com Signed-off-by: -
Kumar, Mahesh authored
don't always use 8 ddb as minimum, instead calculate using proper algorithm. v2: optimizations as per Matt's comments. v3 (by Matt): - Fix boolean logic for !fb test in skl_ddb_min_alloc() - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to improve readability. v4 (by Matt): - Rebase onto recent atomic watermark changes - Slight tweaks to code flow to make the logic more closely match the description in the bspec. v5 (by Matt): - Handle minimum scanline calculation properly for 4 & 8 bpp formats. 8bpp isn't actually possible right now, but it's listed in the bspec so I've included it here for forward compatibility (similar to how we have logic for NV12). v6 (by Matt): - Calculate plane_bpp correctly for non-NV12 formats. (Mahesh) Cc: matthew.d.roper@intel.com Signed-off-by:
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Matt Roper authored
We don't actually read out full plane state during driver startup (only whether the primary plane is enabled/disabled), so all of the src/dest rectangles are invalid at this point. However this calculation was needless anyway since we re-calculate them from scratch on the very first atomic transaction after boot anyway. Signed-off-by:
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Chris Wilson authored
If the VBT says that a certain port should be eDP (and hence fused off from HDMI), but in reality it isn't, we need to try and acquire the HDMI connection instead. So only trust the VBT edp setting if we can connect to an eDP device on that port. Fixes: d2182a66 (drm/i915: Don't register HDMI connectors for eDP ports on VLV/CHV) References: https://bugs.freedesktop.org/show_bug.cgi?id=96288Signed-off-by:
Phidias Chiang <phidias.chiang@canonical.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
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Daniel Vetter authored
This reverts the following patches: d55dbd06 drm/i915: Allow nonblocking update of pageflips. 15c86bdb drm/i915: Check for unpin correctness. 95c2ccdc Reapply "drm/i915: Avoid stalling on pending flips for legacy cursor updates" a6747b73 drm/i915: Make unpin async. 03f476e1 drm/i915: Prepare connectors for nonblocking checks. 2099deff drm/i915: Pass atomic states to fbc update functions. ee7171af drm/i915: Remove reset_counter from intel_crtc. 2ee004f7 drm/i915: Remove queue_flip pointer. b8d2afae drm/i915: Remove use_mmio_flip kernel parameter. 8dd634d9 drm/i915: Remove cs based page flip support. 143f73b3 drm/i915: Rework intel_crtc_page_flip to be almost atomic, v3. 84fc494b drm/i915: Add the exclusive fence to plane_state. 6885843a drm/i915: Convert flip_work to a list. aa420ddd drm/i915: Allow mmio updates on all platforms, v2. afee4d87 Revert "drm/i915: Avoid stalling on pending flips for legacy cursor updates" "drm/i915: Allow nonblocking update of pageflips" should have been split up, misses a proper commit message and seems to cause issues in the legacy page_flip path as demonstrated by kms_flip. "drm/i915: Make unpin async" doesn't handle the unthrottled cursor updates correctly, leading to an apparent pin count leak. This is caught by the WARN_ON in i915_gem_object_do_pin which screams if we have more than DRM_I915_GEM_OBJECT_MAX_PIN_COUNT pins. Unfortuantely we can't just revert these two because this patch series came with a built-in bisect breakage in the form of temporarily removing the unthrottled cursor update hack for legacy cursor ioctl. Therefore there's no other option than to revert the entire pile :( There's one tiny conflict in intel_drv.h due to other patches, nothing serious. Normally I'd wait a bit longer with doing a maintainer revert, but since the minimal set of patches we need to revert (due to the bisect breakage) is so big, time is running out fast. And very soon (especially after a few attempts at fixing issues) it'll be really hard to revert things cleanly. Lessons learned: - Not a good idea to rush the review (done by someone fairly new to the area) and not make sure domain experts had a chance to read it. - Patches should be properly split up. I only looked at the two patches that should be reverted in detail, but both look like the mix up different things in one patch. - Patches really should have proper commit messages. Especially when doing more than one thing, and especially when touching critical and tricky core code. - Building a patch series and r-b stamping it when it has a built-in bisect breakage is not a good idea. - I also think we need to stop building up technical debt by postponing atomic igt testcases even longer. I think it's clear that there's enough corner cases in this beast that we really need to have the testcases _before_ the next step lands. (cherry picked from commit 5a21b665 from drm-intel-next-queeud) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by:
Dave Airlie <airlied@redhat.com> Acked-by:
Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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- 31 May, 2016 3 commits
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Sagar Arun Kamble authored
On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT expired interrupt (bit 9). Host turbo also updates this register in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists. ARAT timer interrupt is needed in GuC for various features. It also facilitates halting GuC and hence achieving RC6. PM interrupt routing will not impact RPS interrupt reception by host as GuC will redirect them. This patch fixes igt test pm_rc6_residency that was failing with guc load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7. v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW) v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW) v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar) Cc: Chris Harris <chris.harris@intel.com> Cc: Zhe Wang <zhe1.wang@intel.com> Cc: Deepak S <deepak.s@intel.com> Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com> Cc: Akash Goel <akash.goel@intel.com> Testcase: igt/pm_rc6_residency Signed-off-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Tested-by:
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Daniel Vetter authored
No dev->struct_mutex anywhere to be seen. Cc: Eric Anholt <eric@anholt.net> Reviewed-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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Daniel Vetter authored
Since my last struct_mutex crusade someone escaped! This already has the advantage that for the common case when someone else holds a ref the unref won't even acquire dev->struct_mutex. And I'm working on code to allow drivers to completely opt-out of any and all dev->struct_mutex usage, but that only works if they use the _unlocked variants everywhere. v2: Drop comment too. v3: Drop the other comment too. Cc: Eric Anholt <eric@anholt.net> Reviewed-by:
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