- 09 Jun, 2019 10 commits
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Yunsheng Lin authored
This patch adds a new hns3_get_new_flow_lvl function to calculate the packet flow level, which is used to decide the interrupt coalescence parameter, in order to make the flow level calculation code more readable and make the future calculation ajdustment easier. Signed-off-by:
Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by:
Peng Li <lipeng321@huawei.com> Signed-off-by:
Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Yunsheng Lin authored
This patch replaces numa_node_id with numa_mem_id when doing buffer reusing checking, because the buffer still can be reused when the buffer is from the nearest node and the local node has no memory attached. Signed-off-by:
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Yunsheng Lin authored
Currently when a GRO packet is assembled by HW, the checksum is modified to reflect the entire packet by HW and skb->ip_summed is set to CHECKSUM_UNNECESSARY, which is not compliant with SW GRO. This patch sets up skb's network and transport header, sets the GRO packet's checksum according to pseudo header and set the skb->ip_summed to CHECKSUM_PARTIAL. This patch also use gso_size to distinguish GRO packet from normal packet, use eth_type_vlan to check the VLAN type and set the SKB_GSO_TCP_FIXEDID according to BD info during HW GRO info processing. Signed-off-by:
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Zhongzhu Liu authored
According to user manual, the maximum size of mailbox responding data is 8 bytes, the macro HCLGE_MBX_MAX_RESP_DATA_SIZE should be defined as 8 instead of 16. Fixes: 9194d18b ("net: hns3: fix the problem that the supported port is empty") Signed-off-by:
Zhongzhu Liu <liuzhongzhu@huawei.com> Signed-off-by:
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Xiaofei Tan authored
This patch logs detail error info of ROCEE ECC and AXI errors for debug purpose, and remove unnecessary reset for ROCEE overflow errors. Signed-off-by:
Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by:
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David S. Miller authored
Grygorii Strashko says: ==================== net: ethernet: ti: netcp: update and enable cpts support The Keystone 2 66AK2HK/E/L 1G Ethernet Switch Subsystems contains The Common Platform Time Sync (CPTS) module which is in general compatible with CPTS module found on TI AM3/4/5 SoCs. So, the basic support for Keystone 2 CPTS is available by default, but not documented and has never been enabled inconfig files. The Keystone 2 CPTS module supports also some additional features like time sync reference (RFTCLK) clock selection through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module, which can modelled as multiplexer clock (this was discussed some time ago [1]). This series adds missed binding documentation for Keystone 2 66AK2HK/E/L CPTS module and enables CPTS for TI Keystone 2 66AK2HK/E/L SoCs with possiblity to select CPTS reference clock. Patch 1: adds the CPTS binding documentation. CPTS bindings are defined in the way that allows CPTS properties to be grouped under "cpts" sub-node. It also defines "cpts-refclk-mux" clock for CPTS RFTCLK selection. Patches 2-3: implement CPTS properties grouping under "cpts" sub-node with backward compatibility support. Patch 4: adds support for time sync reference (RFTCLK) clock selection from DT by adding support for "cpts-refclk-mux" multiplexer clock. Patches 5-9: DT CPTS nodes update for TI Keystone 2 66AK2HK/E/L SoCs. Patch 10: enables CPTS for TI Keystone 2 66AK2HK/E/L SoCs. I grouped all patches in one series for better illustration of the changes, but in general Pateches 1-4 are netdev matarieal (first) and other patches are platform specific. Series can be found at: git@git.ti.com:~gragst/ti-linux-kernel/gragsts-ti-linux-kernel.git branch: net-next-k2e-cpts-refclk Changes in v2: - do reverse christmas tree in cpts_of_mux_clk_setup() - add ack from Richard Cochran v1: https://lkml.org/lkml/2019/6/1/77 [1] https://www.spinics.net/lists/netdev/msg408931.html ==================== Signed-off-by:
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Grygorii Strashko authored
Some CPTS instances, which can be found on KeyStone 2 1G Ethernet Switch Subsystems, can control an external multiplexer that selects one of up to 32 clocks as time sync reference (RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module and can be represented as multiplexer clock. Hence, introduce support for optional cpts-refclk-mux clock, which, once defined will allow to select required CPTS RFTCLK by using assigned-clock-parents DT property in board files. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Acked-by:
Richard Cochran <richardcochran@gmail.com> Signed-off-by:
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Grygorii Strashko authored
Allow to place CPTS properties in the child "cpts" DT node. For backward compatibility - roll-back and read CPTS DT properties from parent node if "cpts" node is not present. Signed-off-by:
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Grygorii Strashko authored
Use devm_get_clk_from_child() instead of devm_clk_get() and this way allow to group CPTS DT properties in sub-node for better code readability and maintenance. Roll-back to devm_clk_get() if devm_get_clk_from_child() fails for backward compatibility. Signed-off-by:
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Grygorii Strashko authored
The Keystone 2 66AK2HK/E/L 1G Ethernet Switch Subsystems contains The Common Platform Time Sync (CPTS) module which is in general compatible with CPTS module found on "legacy" TI AM3/4/5 SoCs. So, the basic support for Keystone 2 CPTS is available by default, but not documented. The Keystone 2 CPTS module supports also some additional features like time sync reference (RFTCLK) clock selection through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module, which is modelled as multiplexer clock. This patch adds missed binding documentation for Keystone 2 66AK2HK/E/L CPTS module. Signed-off-by:
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- 08 Jun, 2019 18 commits
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David S. Miller authored
Vladimir Oltean says: ==================== PTP support for the SJA1105 DSA driver This patchset adds the following: - A timecounter/cyclecounter based PHC for the free-running timestamping clock of this switch. - A state machine implemented in the DSA tagger for SJA1105, which keeps track of metadata follow-up Ethernet frames (the switch's way of transmitting RX timestamps). Clock manipulations on the actual hardware PTP clock will have to be implemented anyway, for the TTEthernet block and the time-based ingress policer. v3 patchset can be found at: https://lkml.org/lkml/2019/6/4/954 Changes from v3: - Made it compile with the SJA1105 DSA driver and PTP driver as modules. - Reworked/simplified/fixed some issues in 03/17 (dsa_8021q_remove_header) and added an ASCII image that illustrates the transformation that is taking place. - Removed a useless check for sja1105_is_link_local from 16/17 (RX timestamping) which also made previous 08/17 patch ("Move sja1105_is_link_local to include/linux") useless and therefore dropped. v2 patchset can be found at: https://lkml.org/lkml/2019/6/2/146 Changes from v2: - Broke previous 09/10 patch (timestamping) into multiple smaller patches. - Every patch in the series compiles. v1 patchset can be found at: https://lkml.org/lkml/2019/5/28/1093 Changes from v1: - Removed the addition of the DSA .can_timestamp callback. - Waiting for meta frames is done completely inside the tagger, and all frames emitted on RX are already partially timestamped. - Added a global data structure for the tagger common to all ports. - Made PTP work with ports in standalone mode, by limiting use of the DMAC-mangling "incl_srcpt" mode only when ports are bridged, aka when the DSA master is already promiscuous and can receive anything. Also changed meta frames to be sent at the 01-80-C2-00-00-0E DMAC. - Made some progress w.r.t. observed negative path delay. Apparently it only appears when the delay mechanism is the delay request-response (end-to-end) one. If peer delay is used (-P), the path delay is positive and appears reasonable for an 1000Base-T link (485 ns in steady state). SJA1105 as PTP slave (OC) with E2E path delay: ptp4l[55.600]: master offset 8 s2 freq +83677 path delay -2390 ptp4l[56.600]: master offset 17 s2 freq +83688 path delay -2391 ptp4l[57.601]: master offset 6 s2 freq +83682 path delay -2391 ptp4l[58.601]: master offset -1 s2 freq +83677 path delay -2391 SJA1105 as PTP slave (OC) with P2P path delay: ptp4l[48.343]: master offset 5 s2 freq +83715 path delay 484 ptp4l[48.468]: master offset -3 s2 freq +83705 path delay 485 ptp4l[48.593]: master offset 0 s2 freq +83708 path delay 485 ptp4l[48.718]: master offset 1 s2 freq +83710 path delay 485 ptp4l[48.844]: master offset 1 s2 freq +83710 path delay 485 ptp4l[48.969]: master offset -5 s2 freq +83702 path delay 485 ptp4l[49.094]: master offset 3 s2 freq +83712 path delay 485 ptp4l[49.219]: master offset 4 s2 freq +83714 path delay 485 ptp4l[49.344]: master offset -5 s2 freq +83702 path delay 485 ptp4l[49.469]: master offset 3 s2 freq +83713 path delay 487 ==================== Signed-off-by:
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Vladimir Oltean authored
This enables the PTP support towards userspace applications such as linuxptp. The switches can timestamp only trapped multicast MAC frames, and therefore only the profiles of 1588 over L2 are supported. TX timestamping can be enabled per port, but RX timestamping is enabled globally. As long as RX timestamping is enabled, the switch will emit metadata follow-up frames that will be processed by the tagger. It may be a problem that linuxptp does not restore the RX timestamping settings when exiting. Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
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Vladimir Oltean authored
Meta frame reception relies on the hardware keeping its promise that it will send no other traffic towards the CPU port between a link-local frame and a meta frame. Otherwise there is no other way to associate the meta frame with the link-local frame it's holding a timestamp of. The receive function is made stateful, and buffers a timestampable frame until its meta frame arrives, then merges the two, drops the meta and releases the link-local frame up the stack. Signed-off-by:
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Vladimir Oltean authored
Without noticing any particular issue, this patch ensures that management traffic is treated with the maximum priority on RX by the switch. This is generally desirable, as the driver keeps a state machine that waits for metadata follow-up frames as soon as a management frame is received. Increasing the priority helps expedite the reception (and further reconstruction) of the RX timestamp to the driver after the MAC has generated it. Signed-off-by:
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Vladimir Oltean authored
This will be used to keep state for RX timestamping. It is global because the switch serializes timestampable and meta frames when trapping them towards the CPU port (lower port indices have higher priority) and therefore having one state machine per port would create unnecessary complications. Signed-off-by:
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Vladimir Oltean authored
This adds support in the tagger for understanding the source port and switch id of meta frames. Their timestamp is also extracted but not used yet - this needs to be done in a state machine that modifies the previously received timestampable frame - will be added in a follow-up patch. Also take the opportunity to: - Remove a comment in sja1105_filter made obsolete by e8d67fa5 ("net: dsa: sja1105: Don't store frame type in skb->cb") - Reorder the checks in sja1105_filter to optimize for the most likely scenario first: regular traffic. Signed-off-by:
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Vladimir Oltean authored
Although meta frames are configured to be sent at SJA1105_META_DMAC (01-80-C2-00-00-0E) which is a multicast MAC address that would also be trapped by the switch to the CPU, were it to receive it on a front-panel port, meta frames are conceptually not link-local frames, they only carry their RX timestamps. The choice of sending meta frames at a multicast DMAC is a pragmatic one, to avoid installing an extra entry to the DSA master port's multicast MAC filter. Signed-off-by:
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Vladimir Oltean authored
This table is used to program the switch to emit "meta" follow-up Ethernet frames (which contain partial RX timestamps) after each link-local frame that was trapped to the CPU port through MAC filtering. This includes PTP frames. Signed-off-by:
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Vladimir Oltean authored
Meta frames are sent on the CPU port by the switch if RX timestamping is enabled. They contain a partial timestamp of the previous frame. They are Ethernet frames with the Ethernet header constructed out of: - SJA1105_META_DMAC - SJA1105_META_SMAC - ETH_P_SJA1105_META The Ethernet payload will be decoded in a follow-up patch. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Vladimir Oltean authored
On TX, timestamping is performed synchronously from the port_deferred_xmit worker thread. In management routes, the switch is requested to take egress timestamps (again partial), which are reconstructed and appended to a clone of the skb that was just sent. The cloning is done by DSA and we retrieve the pointer from the structure that DSA keeps in skb->cb. Then these clones are enqueued to the socket's error queue for application-level processing. Signed-off-by:
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Vladimir Oltean authored
The design of this PHC driver is influenced by the switch's behavior w.r.t. timestamping. It exposes two PTP counters, one free-running (PTPTSCLK) and the other offset- and frequency-corrected in hardware through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either of these for frame timestamps. However, the user manual warns that taking timestamps based on the corrected clock is less than useful, as the switch can deliver corrupted timestamps in a variety of circumstances. Therefore, this PHC uses the free-running PTPTSCLK together with a timecounter/cyclecounter structure that translates it into a software time domain. Thus, the settime/adjtime and adjfine callbacks are hardware no-ops. The timestamps (introduced in a further patch) will also be translated to the correct time domain before being handed over to the userspace PTP stack. The introduction of a second set of PHC operations that operate on the hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat unavoidable, as the TTEthernet core uses the corrected PTP time domain. However, the free-running counter + timecounter structure combination will suffice for now, as the resulting timestamps yield a sub-50 ns synchronization offset in steady state using linuxptp. For this patch, in absence of frame timestamping, the operations of the switch PHC were tested by syncing it to the system time as a local slave clock with: phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01 Signed-off-by:
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Vladimir Oltean authored
These are needed for the situation where the switch driver and the PTP driver are both built as modules. Signed-off-by:
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Vladimir Oltean authored
The incl_srcpt setting makes the switch mangle the destination MACs of multicast frames trapped to the CPU - a primitive tagging mechanism that works even when we cannot use the 802.1Q software features. The downside is that the two multicast MAC addresses that the switch traps for L2 PTP (01-80-C2-00-00-0E and 01-1B-19-00-00-00) quickly turn into a lot more, as the switch encodes the source port and switch id into bytes 3 and 4 of the MAC. The resulting range of MAC addresses would need to be installed manually into the DSA master port's multicast MAC filter, and even then, most devices might not have a large enough MAC filtering table. As a result, only limit use of incl_srcpt to when it's strictly necessary: when under a VLAN filtering bridge. This fixes PTP in non-bridged mode (standalone ports). Otherwise, PTP frames, as well as metadata follow-up frames holding RX timestamps won't be received because they will be blocked by the master port's MAC filter. Linuxptp doesn't help, because it only requests the addition of the unmodified PTP MACs to the multicast filter. This issue is not seen in bridged mode because the master port is put in promiscuous mode when the slave ports are enslaved to a bridge. Therefore, there is no downside to having the incl_srcpt mechanism active there. Signed-off-by:
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Vladimir Oltean authored
>From reading the P/Q/R/S user manual, it appears that TPID is used by the switch for detecting S-tags and TPID2 for C-tags. Their meaning is not clear from the E/T manual. Signed-off-by:
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Vladimir Oltean authored
This is a cosmetic patch, pre-cursor to making another change to the General Parameters Table (incl_srcpt) which does not logically pertain to the sja1105_change_tpid function name, but not putting it there would otherwise create a need of resetting the switch twice. So simply move the existing code into the .port_vlan_filtering callback, where the incl_srcpt change will be added as well. Signed-off-by:
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Vladimir Oltean authored
This removes the existing implementation from tag_sja1105, which was partially incorrect (it was not changing the MAC header offset, thereby leaving it to point 4 bytes earlier than it should have). This overwrites the VLAN tag by moving the Ethernet source and destination MACs 4 bytes to the right. Then skb->data (assumed to be pointing immediately after the EtherType) is temporarily pushed to the beginning of the new Ethernet header, the new Ethernet header offset and length are recorded, then skb->data is moved back to where it was. Signed-off-by:
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Vladimir Oltean authored
This is helpful for e.g. draining per-driver (not per-port) tagger queues. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
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Vladimir Oltean authored
For drivers that use deferred_xmit for PTP frames (such as sja1105), there is no need to perform matching between PTP frames and their egress timestamps, since the sending process can be serialized. In that case, it makes sense to have the pointer to the skb clone that DSA made directly in the skb->cb. It will be used for pushing the egress timestamp back in the application socket's error queue. Signed-off-by:
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- 07 Jun, 2019 4 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller authored
Some ISDN files that got removed in net-next had some changes done in mainline, take the removals. Signed-off-by: -
git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds authored
Pull networking fixes from David Miller: 1) Free AF_PACKET po->rollover properly, from Willem de Bruijn. 2) Read SFP eeprom in max 16 byte increments to avoid problems with some SFP modules, from Russell King. 3) Fix UDP socket lookup wrt. VRF, from Tim Beale. 4) Handle route invalidation properly in s390 qeth driver, from Julian Wiedmann. 5) Memory leak on unload in RDS, from Zhu Yanjun. 6) sctp_process_init leak, from Neil HOrman. 7) Fix fib_rules rule insertion semantic change that broke Android, from Hangbin Liu. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (33 commits) pktgen: do not sleep with the thread lock held. net: mvpp2: Use strscpy to handle stat strings net: rds: fix memory leak in rds_ib_flush_mr_pool ipv6: fix EFAULT on sendto with icmpv6 and hdrincl ipv6: use READ_ONCE() for inet->hdrincl as in ipv4 Revert "fib_rules: return 0 directly if an exactly same rule exists when NLM_F_EXCL not supplied" net: aquantia: fix wol configuration not applied sometimes ethtool: fix potential userspace buffer overflow Fix memory leak in sctp_process_init net: rds: fix memory leak when unload rds_rdma ipv6: fix the check before getting the cookie in rt6_get_cookie ipv4: not do cache for local delivery if bc_forwarding is enabled s390/qeth: handle error when updating TX queue count s390/qeth: fix VLAN attribute in bridge_hostnotify udev event s390/qeth: check dst entry before use s390/qeth: handle limited IPv4 broadcast in L3 TX path net: fix indirect calls helpers for ptype list hooks. net: ipvlan: Fix ipvlan device tso disabled while NETIF_F_IP_CSUM is set udp: only choose unbound UDP socket for multicast when not in a VRF net/tls: replace the sleeping lock around RX resync with a bit lock ... -
git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdmaLinus Torvalds authored
Pull rdma fixes from Jason Gunthorpe: "Things are looking pretty quiet here in RDMA, not too many bug fixes rolling in right now. The usual driver bug fixes and fixes for a couple of regressions introduced in 5.2: - Fix a race on bootup with RDMA device renaming and srp. SRP also needs to rename its internal sys files - Fix a memory leak in hns - Don't leak resources in efa on certain error unwinds - Don't panic in certain error unwinds in ib_register_device - Various small user visible bug fix patches for the hfi and efa drivers - Fix the 32 bit compilation break" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: RDMA/efa: Remove MAYEXEC flag check from mmap flow mlx5: avoid 64-bit division IB/hfi1: Validate page aligned for a given virtual address IB/{qib, hfi1, rdmavt}: Correct ibv_devinfo max_mr value IB/hfi1: Insure freeze_work work_struct is canceled on shutdown IB/rdmavt: Fix alloc_qpn() WARN_ON() RDMA/core: Fix panic when port_data isn't initialized RDMA/uverbs: Pass udata on uverbs error unwind RDMA/core: Clear out the udata before error unwind RDMA/hns: Fix PD memory leak for internal allocation RDMA/srp: Rename SRP sysfs name after IB device rename trigger -
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds authored
Pull arm64 fixes from Will Deacon: "Another round of mostly-benign fixes, the exception being a boot crash on SVE2-capable CPUs (although I don't know where you'd find such a thing, so maybe it's benign too). We're in the process of resolving some big-endian ptrace breakage, so I'll probably have some more for you next week. Summary: - Fix boot crash on platforms with SVE2 due to missing register encoding - Fix architected timer accessors when CONFIG_OPTIMIZE_INLINING=y - Move cpu_logical_map into smp.h for use by upcoming irqchip drivers - Trivial typo fix in comment - Disable some useless, noisy warnings from GCC 9" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Silence gcc warnings about arch ABI drift ARM64: trivial: s/TIF_SECOMP/TIF_SECCOMP/ comment typo fix arm64: arch_timer: mark functions as __always_inline arm64: smp: Moved cpu_logical_map[] to smp.h arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding()
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- 06 Jun, 2019 8 commits
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David S. Miller authored
Robert Hancock says: ==================== Xilinx axienet driver updates (v5) This is a series of enhancements and bug fixes in order to get the mainline version of this driver into a more generally usable state, including on x86 or ARM platforms. It also converts the driver to use the phylink API in order to provide support for SFP modules. Changes since v4: -Use reverse christmas tree variable order ==================== Signed-off-by: -
Robert Hancock authored
Convert this driver to use the phylink API rather than the legacy PHY API. This allows for better support for SFP modules connected using a 1000BaseX or SGMII interface. Signed-off-by:
Robert Hancock <hancock@sedsystems.ca> Signed-off-by:
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Robert Hancock authored
Currently the axienet driver requires the use of a second devicetree node, referenced by an axistream-connected attribute on the Ethernet device node, which contains the resources for the AXI DMA block used by the device. This setup is problematic for a use case we have where the Ethernet and DMA cores are behind a PCIe to AXI bridge and the memory resources for the nodes are injected into the platform devices using the multifunction device subsystem - it's not easily possible for the driver to obtain the platform-level resources from the linked device. In order to simplify that usage model, and simplify the overall use of this driver in general, allow for all of the resources to be kept on one node where the resources are retrieved using platform device APIs rather than device-tree-specific ones. The previous usage setup is still supported if the axistream-connected attribute is specified. Signed-off-by:
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Robert Hancock authored
The axienet driver requires the use of an axistream-connected attribute, but this isn't documented in the devicetree bindings. Document how this attribute is supposed to be used, including the upcoming change to make the usage of this attribute optional. Signed-off-by:
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Robert Hancock authored
This driver was previously using the parent node of the specified PHY node as the device node to register the MDIO bus on. Andrew Lunn pointed out this is wrong as the PHY node is potentially not even underneath the MDIO bus for the current device instance. Find the MDIO node explicitly by looking it up by name under the controller's device node instead. This could potentially break existing device trees if they don't use "mdio" as the name for the MDIO bus, but I did not find any with various searches and Xilinx's examples all use mdio as the name so it seems like this should be relatively safe. Signed-off-by:
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Robert Hancock authored
The mdio child node for the MDIO bus is generally required when using this driver but was not documented other than being shown in the example. Document it as an optional (but usually required) parameter. Signed-off-by:
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Robert Hancock authored
On some platforms, such as iMX6 with PCIe devices, crashes or hangs can occur if the axienet device continues to perform DMA transfers after parent devices/busses have been shut down. Shut down the axienet interface during its shutdown callback in order to avoid this. Signed-off-by:
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Robert Hancock authored
Failing initialization on a missing MAC address property is excessive. We can just fall back to using a random MAC instead, which at least leaves the interface in a functioning state. Signed-off-by:
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