- 27 Jan, 2018 6 commits
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Stephen Boyd authored
Merge branches 'clk-remove-asm-clkdev', 'clk-debugfs-fixes', 'clk-renesas' and 'clk-meson' into clk-next * clk-remove-asm-clkdev: clk: Move __clk_{get,put}() into private clk.h API clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks arch: Remove clkdev.h asm-generic from Kbuild clk: Prepare to remove asm-generic/clkdev.h blackfin: Use generic clkdev.h header * clk-debugfs-fixes: clk: Simplify debugfs registration clk: Fix debugfs_create_*() usage clk: Show symbolic clock flags in debugfs clk: Improve flags doc for of_clk_detect_critical() * clk-renesas: clk: renesas: r8a7796: Add FDP clock clk: renesas: cpg-mssr: Keep wakeup sources active during system suspend clk: renesas: mstp: Keep wakeup sources active during system suspend clk: renesas: r8a77970: Add LVDS clock * clk-meson: clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() clk: meson-axg: make local symbol axg_gp0_params_table static clk: meson-axg: fix return value check in axg_clkc_probe() clk: meson: mpll: use 64-bit maths in params_from_rate clk: meson-axg: add clock controller drivers clk: meson-axg: add clocks dt-bindings required header dt-bindings: clock: add compatible variant for the Meson-AXG clk: meson: make the spinlock naming more specific clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks clk: meson: gxbb: fix wrong clock for SARADC/SANA -
Stephen Boyd authored
* clk-divider-container: clk: divider: fix incorrect usage of container_of Plus fixup sprd/div.c to pass the width too.
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Stephen Boyd authored
* clk-iproc: clk: iproc: Minor tidy up of iproc pll data structures clk: iproc: Allow plls to do minor rate changes without reset clk: iproc: Fix error in the pll post divider rate calculation clk: iproc: Allow iproc pll to runtime calculate vco parameters * clk-mvebu: clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO() * clk-qcom-a53: clk: qcom: Add APCS clock controller support clk: qcom: Add regmap mux-div clocks support clk: qcom: Add A53 PLL support
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Stephen Boyd authored
* clk-at91: clk: at91: pmc: Support backup for programmable clocks clk: at91: pmc: Save SCSR during suspend clk: at91: pmc: Wait for clocks when resuming * clk-imx7ulp: clk: Don't touch hardware when reparenting during registration * clk-axigen: clk: axi-clkgen: Round closest in round_rate() and recalc_rate() clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() * clk-si5351: clk: si5351: _si5351_clkout_reset_pll() can be static clk: si5351: Do not enable parent clocks on probe clk: si5351: Rename internal plls to avoid name collisions clk: si5351: Apply PLL soft reset before enabling the outputs clk: si5351: Add DT property to enable PLL reset clk: si5351: implement remove handler * clk-pxa: clk: pxa: unbreak lookup of CLK_POUT
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Stephen Boyd authored
Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and 'clk-qcom-ipq8074' into clk-next * clk-spreadtrum: clk: sprd: add clocks support for SC9860 clk: sprd: Add dt-bindings include file for SC9860 dt-bindings: Add Spreadtrum clock binding documentation clk: sprd: add adjustable pll support clk: sprd: add composite clock support clk: sprd: add divider clock support clk: sprd: add mux clock support clk: sprd: add gate clock support clk: sprd: Add common infrastructure clk: move clock common macros out from vendor directories * clk-mvebu-dvfs: clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS clk: mvebu: armada-37xx-periph: cosmetic changes * clk-qoriq: clk: qoriq: add more divider clocks support * clk-imx: clk: imx51: uart4, uart5 gates only exist on imx50, imx53 * clk-qcom-ipq8074: clk: qcom: ipq8074: add misc resets for PCIE and NSS dt-bindings: clock: qcom: add misc resets for PCIE and NSS clk: qcom: ipq8074: add GP and Crypto clocks clk: qcom: ipq8074: add NSS ethernet port clocks clk: qcom: ipq8074: add NSS clocks clk: qcom: ipq8074: add PCIE, USB and SDCC clocks clk: qcom: ipq8074: add remaining PLL’s dt-bindings: clock: qcom: add remaining clocks for IPQ8074 clk: qcom: ipq8074: fix missing GPLL0 divider width clk: qcom: add parent map for regmap mux clk: qcom: add read-only divider operations
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Stephen Boyd authored
Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' and 'clk-omap' into clk-next * clk-qcom-alpha-pll: clk: qcom: add read-only alpha pll post divider operations clk: qcom: support for 2 bit PLL post divider clk: qcom: support Brammo type Alpha PLL clk: qcom: support Huayra type Alpha PLL clk: qcom: support for dynamic updating the PLL clk: qcom: support for alpha mode configuration clk: qcom: flag for 64 bit CONFIG_CTL clk: qcom: fix 16 bit alpha support calculation clk: qcom: support for alpha pll properties * clk-check-ops-ptr: clk: check ops pointer on clock register * clk-protect-rate: clk: fix set_rate_range when current rate is out of range clk: add clk_rate_exclusive api clk: cosmetic changes to clk_summary debugfs entry clk: add clock protection mechanism to clk core clk: use round rate to bail out early in set_rate clk: rework calls to round and determine rate callbacks clk: add clk_core_set_phase_nolock function clk: take the prepare lock out of clk_core_set_parent clk: fix incorrect usage of ENOSYS * clk-omap: clk: ti: Drop legacy clk-3xxx-legacy code
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- 10 Jan, 2018 5 commits
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weiyongjun (A) authored
platform_get_resource() may return NULL, add proper check to avoid potential NULL dereferencing. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver update from Geert Uytterhoeven: - Add support for the FDP1-0 module clock on R-Car M3-W * tag 'clk-renesas-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add FDP clock
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Stephen Boyd authored
We don't need a goto here. Drop it. Signed-off-by: -
Geert Uytterhoeven authored
When exposing data access through debugfs, the correct debugfs_create_*() functions must be used, matching the data types. Remove all casts from data pointers passed to debugfs_create_*() functions, as such casts prevent the compiler from flagging bugs. clk_core.rate and .accuracy are "unsigned long", hence casting their addresses to "u32 *" exposed the wrong halves on big-endian 64-bit systems. Fix this by using debugfs_create_ulong() instead. Octal permissions are preferred, as they are easier to read than symbolic permissions. Hence replace "S_IRUGO" by "0444" throughout. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> [sboyd@codeaurora.org: Squash the octal change in too] Signed-off-by:
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Geert Uytterhoeven authored
Currently the virtual "clk_flags" file in debugfs shows the numeric value of the top-level framework flags for the specified clock. Hence the user must manually interpret these values. Moreover, on big-endian 64-bit systems, the wrong half of the value is shown, due to the cast from "unsigned long *" to "u32 *". Fix both issues by showing the symbolic flag names instead. Any non-standard flags are shown as a hex number. Signed-off-by:
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- 05 Jan, 2018 1 commit
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ABE Hiroshige authored
This patch adds FDP1-0 clock to the R8A7796 SoC. Signed-off-by:
ABE Hiroshige <hiroshige.abe.zc@renesas.com> Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: s/fdp0/fdp1-0/] Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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- 04 Jan, 2018 3 commits
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Stephen Boyd authored
We can move these APIs into the private header file now that we don't have any users of the __clk_get() and __clk_put() APIs outside of clkdev.c and clk.c. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: -
Stephen Boyd authored
We'd like to privatize __clk_get(), but the sunxi clk driver is calling this function to keep a reference held on the clk and call clk_prepare_enable() on it. We support this design in the clk core now with the CLK_IS_CRITICAL flag, so let's just use that instead. Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Geert Uytterhoeven authored
The "flags" parameter passed to of_clk_detect_critical() cannot be a pointer to a real clk_core.flags field, as clk_core is private to the clock framework internals. Change the comment to refer to top-level framework flags instead. Signed-off-by:
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- 03 Jan, 2018 3 commits
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Stephen Boyd authored
Now that every architecture is using the generic clkdev.h file and we no longer include asm/clkdev.h anywhere in the tree, we can remove it. Cc: Russell King <linux@armlinux.org.uk> Acked-by:
Arnd Bergmann <arnd@arndb.de> Cc: <linux-arch@vger.kernel.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k] Signed-off-by:
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git://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull Amlogic clk driver update from Jerome Brunet: - Fix overflow in the mpll driver on 32bits arch * tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson: clk: meson: mpll: use 64-bit maths in params_from_rate
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Stephen Boyd authored
Now that all the users of asm/clkdev.h have been replaced with the generic file we can get rid of the asm-generic file as well and implement that code directly where it's used. We only have one caller of __clkdev_alloc(), in clkdev.c so we can easily remove that and drop the include of asm/clkdev.h in linux/clkdev.h by putting the __clk_get/__clk_put inlines in their respective location. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by:
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- 02 Jan, 2018 4 commits
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Stephen Boyd authored
The generic header file is equivalent to the blackfin version, so just use the generic one. Signed-off-by: -
Georgi Djakov authored
Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by:
Amit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Include rcg header for parent_map, drop multiple unneeded includes, add COMPILE_TEST to APCS depends, made tristate/modular] Signed-off-by:
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Georgi Djakov authored
Add support for hardware that can switch both parent clock and divider at the same time. This avoids generating intermediate frequencies from either the old parent clock and new divider or new parent clock and old divider combinations. Signed-off-by:
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Georgi Djakov authored
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by:
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- 28 Dec, 2017 10 commits
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Jerome Brunet authored
divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8f ("clk: allow a clk divider with max divisor when zero") Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by:
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Gomonovych, Vasyl authored
Fix ptr_ret.cocci warnings: drivers/clk/mvebu/armada-37xx-periph.c:362:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by:
Vasyl Gomonovych <gomonovych@gmail.com> Signed-off-by:
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Lori Hikichi authored
There were a few fields in the iproc pll data structures that were holding information that was not true state information. Using stack variables is sufficient and simplifies the structure. There are not any functional changes in this commit. Signed-off-by:
Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by:
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Lori Hikichi authored
The iproc plls are capable of doing small rate changes without the need for a full reset and re-lock procedure. This feature will allow for small tweaks to the PLL rate to occur smoothly. Signed-off-by:
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Lori Hikichi authored
The pll post divider code was using DIV_ROUND_UP when determining the divider value best suited to produce the target frequency. Using DIV_ROUND_CLOSEST will give us better divider values when the division results in a small remainder. Also, change the post divider clock over to the determine_rate api instead of round_rate. Signed-off-by:
Simran Rai <ssimran@broadcom.com> Signed-off-by:
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Lori Hikichi authored
Add the ability for the iproc pll to calculate the pll parameters at runtime instead of only using predefined tables. This ability allows the clock users to select from the full range of vco frequencies. The old method of table based programming is retained so that existing users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM will need to be set to enable the new runtime calculation method. Currently, this is only being enabled for the audio pll. This feature also revealed a problem with the driver using the round_rate api. The round_rate api does not allow for frequencies larger than 2^31 to be returned. Those large frequencies are interpreted as an error code. Therefore, we are moving to the determine_rate api which solves this problem. Signed-off-by:
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Wu Fengguang authored
Fixes: b26ff127 ("clk: si5351: Apply PLL soft reset before enabling the outputs") Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Igor Grinberg authored
Since switching to clk drivers, the CLK_POUT cannot be searched for by clk_get() API and thus it returns with ENOENT. Register it with the clk_lookup and thus unbreak the users of it. Signed-off-by:
Igor Grinberg <grinberg@compulab.co.il> Acked-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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weiyongjun (A) authored
Fixes the following sparse warning: drivers/clk/meson/axg.c:260:25: warning: symbol 'axg_gp0_params_table' was not declared. Should it be static? Signed-off-by:
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weiyongjun (A) authored
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 78b4af31 ("clk: meson-axg: add clock controller drivers") Signed-off-by:
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- 23 Dec, 2017 1 commit
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Martin Blumenstingl authored
"rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b SoCs if the "remainder" (after the division operation) is greater than 262143Hz. This is likely to happen since the input clock for the MPLLs on Meson8 and Meson8b is "fixed_pll", which is running at a rate of 2550MHz. One example where this was observed to be problematic was the Ethernet clock calculation (which takes MPLL2 as input). When requesting a rate of 125MHz there is a remainder of 2500000Hz. The resulting MPLL2 rate before this patch was 127488329Hz. The resulting MPLL2 rate after this patch is 124999103Hz. Commit b609338b ("clk: meson: mpll: use 64bit math in rate_from_params") already fixed a similar issue in rate_from_params. Fixes: 007e6e5c ("clk: meson: mpll: add rw operation") Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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- 22 Dec, 2017 7 commits
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Sergej Sawazki authored
The si5351 driver should not prepare or enable other clocks in the tree on probe. Let the clients decide when to prepare or enable the clocks. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by:
Sergej Sawazki <ce3a@gmx.de> [sboyd@codeaurora.org: Remove most of the .remove function too] Signed-off-by:
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Sergej Sawazki authored
This drivers probe fails due to a clock name collision if a clock named 'plla' or 'pllb' is already registered when registering this drivers internal plls. Fix it by renaming internal plls to avoid name collisions. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by:
Sergej Sawazki <sergej@taudac.com> Signed-off-by:
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Sergej Sawazki authored
The "Si5351A/B/C Data Sheet" states to apply a PLL soft reset before enabling the output clocks [1]. This is required to get a deterministic phase relationship between the output clocks. Without resetting the PLL, the phase relationship between the clocks is unpredictable. Fix this by resetting the PLL in si5351_clkout_prepare(). References: [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf Figure 12 ("I2C Programming Procedure") Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by:
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Sergej Sawazki authored
Add optional output clock DT property to enable PLL reset when a clock output is enabled. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by:
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Alexey Khoroshilov authored
The driver has no remove function, so it does not cleanup resources that are not under devm management. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by:
Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by:
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Lars-Peter Clausen authored
To minimize the rounding error round to the closest integer when calculating the result in the recalc_rate() and set_rate() callbacks. Also in order to improve precision multiply first and then divide. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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Lars-Peter Clausen authored
If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by:
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