- 18 Jul, 2018 29 commits
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Boris Brezillon authored
The MTD_NAND_GPMI_NAND entry is already defined in an 'if MTD_NAND' block, no need to add an extra "depends on MTD_NAND". Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com>
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Abhishek Sahu authored
NAND parts can have bitflips in an erased page due to the process technology used. In this case, QCOM NAND controller is not able to identify that page as an erased page. Currently the driver calls nand_check_erased_ecc_chunk() for identifying the erased pages but this won’t work always since the checking is being with ECC engine returned data. In case of bitflips, the ECC engine tries to correct the data and then it generates the uncorrectable error. Now, this data is not equal to original raw data. For erased CW identification, the raw data should be read again from NAND device and this nand_check_erased_ecc_chunk function() should be called for raw data only. Now following logic is being added to identify the erased codeword bitflips. 1. In most of the cases, not all the codewords will have bitflips and only single CW will have bitflips. So, there is no need to read the complete raw page data. The NAND raw read can be scheduled for any CW in page. The NAND controller works on CW basis and it will update the status register after each CW read. Maintain the bitmask for the CW which generated the uncorrectable error. 2. Do raw read for all the CW's which generated the uncorrectable error. 3. Both DATA and OOB need to be checked for number of 0. The top-level API can be called with only data buf or OOB buf so use chip->databuf if data buf is null and chip->oob_poi if OOB buf is null for copying the raw bytes temporarily. 4. For each CW, check the number of 0 in cw_data and usable oob bytes, The bbm and spare (unused) bytes bit flip won’t affect the ECC so don’t check the number of bitflips in this area. Signed-off-by:
Abhishek Sahu <absahu@codeaurora.org> Signed-off-by:
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Colin Ian King authored
Variable payload_virt is being assigned but is never used hence it is redundant and can be removed. Cleans up clang warning: warning: variable 'payload_virt' set but not used [-Wunused-but-set-variable] Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Miquel Raynal authored
nand_release() should not be called on an MTD device that has not been registered. While it should work thanks to the checks done in mtd_device_unregister() it's a bad practice to cleanup/release something that has not previously been initialized/allocated. Rework the error path to follow this rule. Signed-off-by: -
Masahiro Yamada authored
This commit improves the ->setup_data_interface() hook. The denali_setup_data_interface() needs the frequency of clk_x and the ratio of clk_x / clk. The latter is currently hardcoded in the driver, like this: #define DENALI_CLK_X_MULT 6 The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just chose 6 because it is the most defensive value, but it is not optimal. By getting the clock rate of both "clk" and "clk_x", the driver can compute the timing values more precisely. To not break the existing platforms, the fallback value, 50 MHz is provided. It is true for all upstreamed platforms. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
Richard Weinberger <richard@nod.at> Tested-by:
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Masahiro Yamada authored
Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run This commit supports these named clocks to represent the real hardware. For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected. Signed-off-by:
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Masahiro Yamada authored
Commit 30f9f2fb ("mtd: denali: add a DT driver") supported the clock enablement, but did not document it in the DT binding. In addition to the existing clock, this commit adds more clocks based on the IP specification. According to the Denali User's Guide, this IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run The driver should accept the current single clock for the backward compatibility, but the DT binding should represent the real hardware, and future platforms must follow this. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Masahiro Yamada authored
The probe function references &pdev->dev many times, and I will add more soon. Add 'dev' as a shorthand. Signed-off-by:
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Martin Kaiser authored
Using the sysfs unbind, bind nodes, mxcnd_probe and mxcnd_probe_dt can potentially be called at any time. After the __init functions are cleaned, mxcnd_probe_dt is no longer available. Calling it anyway causes a crash. mxcnd_probe used to be marked as __init, this was removed years ago. Remove the __init qualifier from from mxcnd_probe_dt as well. Fixes: 06f25510 ("mtd: remove use of __devinit") Signed-off-by:
Martin Kaiser <martin@kaiser.cx> Reviewed-by:
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Miquel Raynal authored
MX35LF2GE4AB is almost identical to MX35LF1GE4AB except it has 2 times more eraseblocks per LUN and exposes 2 planes instead of 1. Signed-off-by:
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Boris Brezillon authored
Add minimal support for the MX35LF1GE4AB SPI NAND chip. Signed-off-by:
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Frieder Schrempf authored
Add support for the W25M02GV chip. Signed-off-by:
Frieder Schrempf <frieder.schrempf@exceet.de> Signed-off-by:
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Peter Pan authored
Add a basic driver for Micron SPI NANDs. Only one device is supported right now, but the driver will be extended to support more devices afterwards. Signed-off-by:
Peter Pan <peterpandong@micron.com> Signed-off-by:
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Boris Brezillon authored
Add bindings for SPI NAND chips. Signed-off-by:
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Peter Pan authored
Add a SPI NAND framework based on the generic NAND framework and the spi-mem infrastructure. In its current state, this framework supports the following features: - single/dual/quad IO modes - on-die ECC Signed-off-by:
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Abhishek Sahu authored
Function nand_ecc_choose_conf() will be help for all the cases, so other helper functions can be made static. nand_check_ecc_caps(): Invoke nand_ecc_choose_conf() with both chip->ecc.size and chip->ecc.strength value set. nand_maximize_ecc(): Invoke nand_ecc_choose_conf() with NAND_ECC_MAXIMIZE flag. nand_match_ecc_req(): Invoke nand_ecc_choose_conf() with either chip->ecc.size or chip->ecc.strength value set and without NAND_ECC_MAXIMIZE flag. CC: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: -
Abhishek Sahu authored
Make separate function to perform raw read for one codeword and call this function multiple times for each codeword in case of raw page read. This separate function will help in subsequent patches related with erased codeword bitflip detection. It will decrease throughput for raw page read. Raw page read is used for debug purpose so it won't affect normal flash operations. Signed-off-by:
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Abhishek Sahu authored
Currently there is no error checking for raw read. For raw reads, there won’t be any ECC failure but the operational failures are possible, so schedule the NAND_FLASH_STATUS read after each codeword. Signed-off-by:
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Abhishek Sahu authored
Fix value returned by ->read_page_raw() to be the actual operation status, instead of always 0. Signed-off-by:
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Abhishek Sahu authored
QCOM NAND controller layout protects available OOB data bytes with ECC also so when ecc->write_oob() is being called then it can't update just OOB bytes. Currently, it first reads the last codeword which includes old OOB bytes. Then it updates the old OOB bytes with new ones and then again writes the codeword back. The reading codeword is unnecessary since user is responsible to have these bytes cleared to 0xFF. This patch removes the read part and updates the OOB bytes with data area padded with OxFF. Signed-off-by:
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Abhishek Sahu authored
read_page and read_oob both calls the read_page_ecc function. The QCOM NAND controller protect the OOB available bytes with ECC so read errors should be checked for read_oob also. This patch moves the error checking code inside read_page_ecc so caller does not have to check explicitly for read errors. Signed-off-by:
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Abhishek Sahu authored
parse_read_errors can be called with only oob_buf in which case data_buf will be NULL. If data_buf is NULL, then don’t treat this page as completely erased in case of ECC uncorrectable error for RS ECC. For BCH ECC, the controller itself tells regarding erased page in status register. Signed-off-by:
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Abhishek Sahu authored
Following is the flow in the HW if controller tries to read erased page: 1. First ECC uncorrectable error will be generated from ECC engine since ECC engine first calculates the ECC with all 0xff and match the calculated ECC with ECC code in OOB (which is again all 0xff). 2. After getting ECC error, erased CW detection logic will be applied which is different for BCH and RS ECC a. For BCH, HW checks if all the bytes in page are 0xff and then it updates the status in separate register NAND_ERASED_CW_DETECT_STATUS. b. For RS ECC, the HW reports the same error when reading an erased CW, but it notifies that it is an erased CW by placing special characters at certain offsets in the buffer. So the erased CW detect status should be checked only if ECC engine generated the uncorrectable error. Currently for all other operational errors also (like TIMEOUT, MPU errors, etc.), the erased CW detect logic is being applied so fix this and return EIO for other operational errors. Signed-off-by: -
Abhishek Sahu authored
The BAM has 3 channels - tx, rx and command. command channel is used for register read/writes, tx channel for data writes and rx channel for data reads. Currently, the driver assumes the transfer completion once it gets all the command descriptors completed. Sometimes, there is race condition between data channel (tx/rx) and command channel completion. In these cases, the data present in buffer is not valid during small window between command descriptor completion and data descriptor completion. This patch generates NAND transfer completion when both (Data and Command) DMA channels have completed all its DMA descriptors. It assigns completion callback in last DMA descriptors of that channel and wait for completion. Fixes: 8d6b6d7e ("mtd: nand: qcom: support for command descriptor formation") Cc: stable@vger.kernel.org Signed-off-by:
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Abhishek Sahu authored
Currently the driver uses the ECC strength specified in DT. The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same kind of board can have different NAND parts so use the ECC strength from device parameters if it is not specified in DT. Signed-off-by:
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Abhishek Sahu authored
QCOM NAND controller supports only one step size (512) so nand-ecc-step-size DT property is redundant. This property can be removed and ecc step size can be assigned with 512 value. Signed-off-by:
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Abhishek Sahu authored
1. If nand-ecc-strength specified in DT, then controller will use this ECC strength otherwise ECC strength will be calculated according to chip requirement and available OOB size. 2. QCOM NAND controller supports only one step size (512 bytes) but nand-ecc-step-size is required property in DT. This DT property can be removed and ecc step size can be assigned in driver with 512 bytes value. Signed-off-by:
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Abhishek Sahu authored
Use the NAND core helper function nand_ecc_choose_conf to tune the ECC parameters instead of the function locally defined. Signed-off-by:
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Abhishek Sahu authored
commit 2c8f8afa ("mtd: nand: add generic helpers to check, match, maximize ECC settings") provides generic helpers which drivers can use for setting up ECC parameters. Since same board can have different ECC strength nand chips so following is the logic for setting up ECC strength and ECC step size, which can be used by most of the drivers. 1. If both ECC step size and ECC strength are already set (usually by DT) then just check whether this setting is supported by NAND controller. 2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength supported by NAND controller. 3. Otherwise, try to match the ECC step size and ECC strength closest to the chip's requirement. If available OOB size can't fit the chip requirement then select maximum ECC strength which can be fit with available OOB size. This patch introduces nand_ecc_choose_conf function which calls the required helper functions for the above logic. The drivers can use this single function instead of calling the 3 helper functions individually. Signed-off-by:
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- 02 Jul, 2018 11 commits
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Chris Packham authored
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the revision number field of the ONFI parameter page. Rather than rejecting these outright assume ONFI version 1.0 if the revision number is 00 00. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by:
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Chris Packham authored
Add defines for the ONFI version bits and use them in nand_flash_detect_onfi(). Signed-off-by:
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Chris Packham authored
This is called after the ONFI parameter page checksum is verified and allows us to override the contents of the parameter page. Suggested-by:
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Chris Packham authored
>From the controllers point of view this is the same as no or software only ECC. Signed-off-by:
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Stefan Agner authored
Add support for the NAND flash controller found on NVIDIA Tegra 2 SoCs. This implementation does not make use of the command queue feature. Regular operations using ->exec_op() use PIO mode for data transfers. Raw, ECC and OOB read/writes make use of the DMA mode for data transfer. Signed-off-by:
Lucas Stach <dev@lynxeye.de> Signed-off-by:
Stefan Agner <stefan@agner.ch> Reviewed-by:
Dmitry Osipenko <digetx@gmail.com> Reviewed-by:
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Stefan Agner authored
This adds the devicetree binding for the Tegra 2 NAND flash controller. Signed-off-by:
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Stefan Agner authored
Allow to define a NAND chip as a boot device. This can be helpful for the selection of the ECC algorithm and strength in case the boot ROM supports only a subset of controller provided options. Signed-off-by:
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Stefan Agner authored
Add Reed-Solomon (RS) to the enumeration of ECC algorithms. Signed-off-by:
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Martin Blumenstingl authored
The datasheet of the H27UCG8T2BTR states that this chip has a page size of "16,384 + 1,280(Spare) bytes". The description of the "4th Byte of Device Identifier Description" indicates that bits 6, 3 and 2 are encoding the "Redundant Area Size / 8KB", where 640 bytes is a value of 0x6 (110 in binary notation). hynix_nand_extract_oobsize decodes an OOB size of 640 bytes for this chip. Kernel boot log extract before this patch: nand: Could not find valid ONFI parameter page; aborting nand: device found, Manufacturer ID: 0xad, Chip ID: 0xde nand: Hynix NAND 8GiB 3,3V 8-bit nand: 8192 MiB, MLC, erase size: 4096 KiB, page size: 16384, OOB size: 640 However, based on the description in the datasheet we need to multiply the OOB size with 2, because it's "640 spare bytes per 8192 bytes page size" and this NAND chip has a page size of 16384 (= 2 * 8192). After this patch the kernel boot log reports: nand: Could not find valid ONFI parameter page; aborting nand: device found, Manufacturer ID: 0xad, Chip ID: 0xde nand: Hynix NAND 8GiB 3,3V 8-bit nand: 8192 MiB, MLC, erase size: 4096 KiB, page size: 16384, OOB size: 1280 Signed-off-by:Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
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Boris Brezillon authored
Even if we can't update ecc_stats.corrected with an accurate value we should at least increase the number of bitflips so that MTD users can know that there was some bitflips. Just add chip->ecc.strength to mtd->ecc_stats.corrected which should account for the worst case situation. Signed-off-by:
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Peter Rosin authored
On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND flash accesses have a tendency to cause display disturbances. Add a module param to disable DMA from the NAND controller, since that fixes the display problem for me. Signed-off-by:
Peter Rosin <peda@axentia.se> Reviewed-by:
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