- 16 Jun, 2017 2 commits
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Stephen Boyd authored
It isn't used outside of this file right now. Signed-off-by:Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches from Maxime Ripard: Some new clock units are supported, for the display clocks unsed in the newer SoCs, and the A83T PRCM. There is also a bunch of minor fixes for clocks that are not used by anyone, and reworks needed by drivers that will land in 4.13. * tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits) clk: sunxi-ng: Move all clock types to a library clk: sunxi-ng: a83t: Add support for A83T's PRCM dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t clk: sunxi-ng: a83t: Fix audio PLL divider offset clk: sunxi-ng: a83t: Fix PLL lock status register offset clk: sunxi-ng: Add driver for A83T CCU clk: sunxi-ng: Support multiple variable pre-dividers dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: sun5i: Export video PLLs clk: sunxi-ng: mux: Re-adjust parent rate clk: sunxi-ng: mux: Change pre-divider application function prototype clk: sunxi-ng: mux: split out the pre-divider computation code clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT clk: sunxi-ng: div: Switch to divider_round_rate clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate clk: divider: Make divider_round_rate take the parent clock clk: sunxi-ng: explicitly include linux/spinlock.h clk: sunxi-ng: add support for DE2 CCU ...
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- 14 Jun, 2017 5 commits
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Stephen Boyd authored
* clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
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Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Allwinner clock fixes for 4.12 Some fixes that fix some bindings that went in 4.12, fix a few reset and clock offsets and a build error fix * tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
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Stephen Boyd authored
Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull samsung clk driver updates from Sylwester Nawrocki - conversion to the clk_hw API - definitions and fixes of exynos5420 SoC audio subsystem related clocks * tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos542x: Add EPLL rate table clk: samsung: Add missing exynos5420 audio related clocks clk: samsung: Add enable/disable operation for PLL36XX clocks clk: samsung: s5pv210-audss: Convert to the new clk_hw API clk: samsung: exynos-clkout: Convert to the new clk_hw API clk: samsung: exynos-audss: Convert to the new clk_hw API clk: samsung: Convert common drivers to the new clk_hw API clk: samsung: Add local variable to match its purpose clk: samsung: Remove dead code
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Stephen Boyd authored
Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk table and the usual bunch of some new clock-ids and some clocks marked as critical. * tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark some special clk as critical on rk3368 clk: rockchip: mark noc and some special clk as critical on rk3288 clk: rockchip: mark noc and some special clk as critical on rk3228 clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036 clk: rockchip: add clock controller for rk3128 dt-bindings: add bindings for rk3128 clock controller clk: rockchip: export more rk3228 clocks ids clk: rockchip: add ids for rk3399 testclks used for camera handling clk: rockchip: add dt-binding header for rk3128 clk: rockchip: fix up the RK3228 clk cpu setting table clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399
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Tero Kristo authored
In K2G, the clock handling is done through firmware executing on a separate core. Linux kernel needs to communicate to the firmware through TI system control interface to access any power management related resources, including clocks. The keystone sci-clk driver does this, by communicating to the firmware through the TI SCI driver. The driver adds support for registering clocks through DT, and basic required clock operations like prepare/get_rate, etc. Signed-off-by:
Tero Kristo <t-kristo@ti.com> [sboyd@codeaurora.org: Make ti_sci_init_clocks() static] Signed-off-by:
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- 13 Jun, 2017 1 commit
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Tero Kristo authored
Add a clock implementation, TI SCI clock, that will hook to the common clock framework, and allow each clock to be controlled via TI SCI protocol. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 09 Jun, 2017 6 commits
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Sylwester Nawrocki authored
A specific clock rate table is added for EPLL so it is possible to set frequency of the EPLL output clock as multiple of various audio sampling rates. Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Sylwester Nawrocki authored
This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Reviewed-by:
Chanwoo Choi <cw00.choi@samsung.com> Tested-by:
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Sylwester Nawrocki authored
The existing enable/disable ops for PLL35XX are made more generic and used also for PLL36XX. This fixes issues in the kernel with PLL36XX PLLs when the PLL has not been already enabled by bootloader. Reviewed-by:
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Marek Szyprowski authored
Clock providers should use the new struct clk_hw based API, so convert Samsung S5PV210 Audio Subsystem clock provider to the new approach. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
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Marek Szyprowski authored
Clock providers should use the new struct clk_hw based API, so convert Exynos CLKOUT clock provider to the new approach. Signed-off-by:
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Marek Szyprowski authored
Clock providers should use the new struct clk_hw based API, so convert Exynos Audio Subsystem clock provider to the new approach. Signed-off-by:
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- 07 Jun, 2017 25 commits
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Marek Szyprowski authored
Clock providers should use the new struct clk_hw based API, so convert Samsung clock providers and their helper functions to the new approach. Signed-off-by:
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Marek Szyprowski authored
Add new variable to avoid using clk pointer for different purposes across the exynos_register_cpu_clock() function. This will help in future rewrite for the new clk_hw API. Signed-off-by:
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Marek Szyprowski authored
samsung_clk_register_pll2550x() function is not used anymore, so remove its declaration. Signed-off-by:
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Stephen Boyd authored
We've run into kconfig missing dependency errors in the sunxi-ng code a couple times now. Each time the fix is to find the missing select statement and add it to the Kconfig entry for a particular SoC driver. Given that all this code is builtin (non-modular) we don't need to do this complicated dependency tracking in Kconfig. Instead we can move all the "library"ish code to be compiled as lib-y instead of obj-y, let the linker throw away unused code in the resulting vmlinux, and drop all the Kconfig stuff we use to track clock types. Suggested-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Chen-Yu Tsai authored
The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. The PRCM also has controls for various power domains. These are not supported yet. Signed-off-by:
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Arnd Bergmann authored
We get a link error when CCU_MULT is not set with the newly added driver: drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_mult_ops' drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.3+0x4): undefined reference to `ccu_mult_ops' Fixes: 46b492116666 ("clk: sunxi-ng: Add driver for A83T CCU") Signed-off-by: -
Chen-Yu Tsai authored
The divider of the audio PLL has an offset of 1. Fix this in the driver. Signed-off-by:
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Chen-Yu Tsai authored
The offset for the PLL lock status register was incorrectly set to 0x208, which actually points to an unused register. The correct register offset is 0x20c. Signed-off-by:
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Chen-Yu Tsai authored
The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Also, the MMC2 module clock supports switching to a "new timing" mode. This mode divides the clock output by half, and disables the CCU based clock delays. The MMC controller must be configure to the same mode, and then use its internal clock delays. This driver does not support runtime switching of the timing modes. Instead, the new timing mode is enforced at probe time. Consumers can check which mode is active by trying to get the current phase delay of the MMC2 phase clocks, which will return -ENOTSUPP if the new timing mode is active. Signed-off-by:
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Chen-Yu Tsai authored
On the A83T, the AHB1 clock has a shared pre-divider on the two PLL-PERIPH clock parents. To support such instances of shared pre-dividers, this patch extends the mux clock type to support multiple variable pre-dividers. As the pre-dividers are only used to calculate the rate, but do not participate in the factorization process, this is fairly straightforward. Signed-off-by:
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Chen-Yu Tsai authored
The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Signed-off-by:
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Wei Yongjun authored
PTR_ERR should access the value just tested by IS_ERR, otherwise the wrong error code will be returned. Fixes: b0d9a4bd52bd ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by:Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Maxime Ripard authored
The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by:
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Maxime Ripard authored
Currently, the parent rate given back to the clock framework in our request is the original parent rate we calculated before trying to round the rate of our clock. This works fine unless our clock also changes its parent rate, in which case we will simply ignore that change and still use the previous parent rate. Create a new function to re-adjust the parent rate to take the pre-dividers into account, and give that back to the clock framework. Signed-off-by:
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Maxime Ripard authored
The current function name is a bit confusing, and doesn't really allow to create an explicit function to reverse the operation. We also for now change the parent rate through a pointer, while we don't return anything. In order to be less confusing, and easier to use for downstream users, change the function name to something hopefully clearer, and return the adjusted rate instead of changing the pointer. Signed-off-by:
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Maxime Ripard authored
The pre-divider retrieval code was merged into the function to apply the current pre-divider onto the parent clock rate so that we can use that adjusted value to do our factors computation. However, since we'll need to do the reverse operation, we need to split out that code into a function that will be shared. Signed-off-by:
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Maxime Ripard authored
The current code only rely on the parent to change its rate in the case where CLK_SET_RATE_PARENT is set. However, some clock rates might be obtained only through a modification of the parent and the clock divider. Just rely on the round rate of the clocks to give us the best computation that might be achieved for a given rate. round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the functions already do that if they modify the parent, or don't modify the praents at all. Signed-off-by:
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Maxime Ripard authored
divider_round_rate_parent already evaluates changing the parent rate if CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's just use it. Signed-off-by:
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Maxime Ripard authored
The clocks might need to modify their parent clocks. In order to make that possible, give them access to the parent clock being evaluated, and to a pointer to the parent rate so that they can modify it if needed. Signed-off-by:
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Maxime Ripard authored
So far, divider_round_rate only considers the parent clock returned by clk_hw_get_parent. This works fine on clocks that have a single parents, this doesn't work on muxes, since we will only consider the first parent, while other parents may totally be able to provide a better combination. Clocks in that case cannot use divider_round_rate, so would have to come up with a very similar logic to work around it. Instead of having to do something like this, and duplicate that logic everywhere, create a divider_round_rate parent to allow caller to give an additional parameter for the parent clock to consider. Reviewed-by:
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Tobias Klauser authored
ccu_reset.h and ccu_reset.c use spinlock_t and associated functions but rely on implict inclusion of linux/spinlock.h which means that changes in other headers could break the build. Thus, add an explicit include. Signed-off-by:
Tobias Klauser <tklauser@distanz.ch> Acked-by:
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Icenowy Zheng authored
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock management unit for its subunits, like the DE CCU in A80. Add a sunxi-ng style driver for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
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Icenowy Zheng authored
Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by:
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Fabio Estevam authored
Commit ad149724 ("clk: imx7d: Fix the powerdown bit location of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case. Fix it accordingly to avoid a kernel hang. Reported-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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- 05 Jun, 2017 1 commit
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Alexandre Belloni authored
Fix missing } Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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