- 02 Jun, 2017 1 commit
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Michael Turquette authored
Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next clk: renesas: Updates for v4.13 - Add more module clocks for R-Car H3 ES2.0 and M3-W, - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support for module resets, which are not supported by the existing driver, - Rework Kconfig and Makefile logic, - Small fixes and cleanups.
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- 01 Jun, 2017 13 commits
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Bryan O'Donoghue authored
When failing to set a clock the printout emitted is incorrect. "u32 rate" is formatted as %d and should be %u whereas "unsigned long clk_set_rate()" is formatted as %ld and should be %lu as per Documentation/printk-formats.txt. Fixes: 2885c3b2 ("clk: Show correct information when fail to set clock rate") Signed-off-by:
Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Sudeep Holla authored
The frequencies above the maximum value of signed integer(i.e. 2^31 -1) will overflow with the current code. This patch fixes the return type of __scpi_dvfs_round_rate from 'int' to 'unsigned long'. Fixes: cd52c2a4 ("clk: add support for clocks provided by SCP(System Control Processor)") Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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Scott Wood authored
ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. If a second input clock, named "coreclk", is present, this clock will be used for the core PLLs. Signed-off-by:
Scott Wood <oss@buserror.net> Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Scott Wood authored
ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. Update the qoriq-clock binding to allow a second input clock, named "coreclk". If present, this clock will be used for the core PLLs. Signed-off-by:
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Alexandre Belloni authored
clk_generated_startup is called after clk_hw_register. So the first call to get_parent will not have the correct value (i.e. 0) and because this is cached, it may never be updated. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: df70aeef ("clk: at91: add generated clock driver") Signed-off-by:
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Fabio Estevam authored
According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Ralph Sennhauser authored
The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the list of supported CPU frequencies. Also update multiplier and divisor for the l2clk and ddrclk. Noticed by the following warning: [ 0.000000] Selected CPU frequency (16) unsupported Signed-off-by:
Ralph Sennhauser <ralph.sennhauser@gmail.com> Reviewed-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Michael Turquette authored
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Gregory CLEMENT authored
As for cp110, the initial intent when the binding of the ap806 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Acked-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/cc8c8c40fa4c4e71133033358992ec38e5aa2be5.1496239589.git-series.gregory.clement@free-electrons.com
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Gregory CLEMENT authored
As it was done for the cp110, this patch modifies the way the clock names are created. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
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Gregory CLEMENT authored
Instead of using &pdev->dev all over the place, introduce a pointer variable for it. Signed-off-by:
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Gregory CLEMENT authored
This patch updates the documentation according to the changes made in the patch "clk: mvebu: ap806: introduce a new binding" Acked-by:
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Gregory CLEMENT authored
This patch updates the documentation according to the change made in the patch "clk: mvebu: ap806: do not depend anymore of the *-clock-output-names": the clock names are no more part of the binding. Acked-by:
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- 25 May, 2017 2 commits
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git://github.com/baylibre/clk-mesonMichael Turquette authored
KConfig fix: - clk: meson: gxbb: fix build error without RESET_CONTROLLER
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Boris Brezillon authored
AHB BIST gate is actually controlled with bit 7. This bug was detected while trying to use the NAND controller which is using the DMA engine to transfer data to the NAND. Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit, the core was disabling the DMA engine clock as part of its 'disable unused clks' procedure, which was causing all DMA transfers to fail after this point. Fixes: 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver") Cc: stable@vger.kernel.org Reported-by:
Angus Ainslie <angus@akkea.ca> Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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- 24 May, 2017 12 commits
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Geert Uytterhoeven authored
Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: -
Geert Uytterhoeven authored
Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: -
Geert Uytterhoeven authored
Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: -
Geert Uytterhoeven authored
Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by:Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Geert Uytterhoeven authored
Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: -
Geert Uytterhoeven authored
Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: -
Geert Uytterhoeven authored
Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: -
Geert Uytterhoeven authored
Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: -
Geert Uytterhoeven authored
Document use of the Renesas Clock Pulse Generator / Module Standby and Software Reset DT Bindings for various member of the R-Car Gen2 family (H2, M2-W, V2H, M2-N, and E2). Signed-off-by:
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Geert Uytterhoeven authored
The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by:Simon Horman <horms+renesas@verge.net.au> Acked-by:
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Geert Uytterhoeven authored
Coccinelle warns: drivers/clk/renesas/renesas-cpg-mssr.c:323:14-21: ERROR: PTR_ERR applied after initialization to constant on line 260 Initialize clk using ERR_PTR(-ENOTSUPP) instead of NULL to fix this. Reported-by:kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
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- 16 May, 2017 1 commit
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Tobias Regnery authored
With CONFIG_RESET_CONTROLLER=n we see the following link error in the meson gxbb clk driver: drivers/built-in.o: In function 'gxbb_aoclkc_probe': drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register' Fix this by selecting the reset controller subsystem. Fixes: f8c11f79 ("clk: meson: Add GXBB AO Clock and Reset controller driver") Signed-off-by:
Tobias Regnery <tobias.regnery@gmail.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> [narmstrong: Added fixes-by tag] Signed-off-by:
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- 15 May, 2017 11 commits
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Geert Uytterhoeven authored
Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual Rev. 0.53E. These have no user-visible effect, as the clock frequencies stay the same. Fixes: 5573d194 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by:
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Geert Uytterhoeven authored
The pm_subsys_data.clock_list member exists only if CONFIG_PM_CLK=y. Hence direct accesses to this field break compile-testing on platforms where CONFIG_PM_CLK=n. To fix this, use the pm_clk_no_clocks() helper instead, for which a dummy version is provided if CONFIG_PM_CLK=n. Signed-off-by:
Simon Horman <simon.horman@netronome.com>
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Geert Uytterhoeven authored
R-Car V2H does not have "DIV6" programmable clocks, hence there is no need to build clk-div6.o. Signed-off-by:
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Takeshi Kihara authored
Add the "intc-ex" clock to the R8A7796 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. [takeshi.kihara.df: Ported from commit f099aa07 ("clk: shmobile: r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c] Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by:
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Harunobu Kurokawa authored
This patch adds PCIEC{0,1} clocks for R8A7796 SoC. Signed-off-by:Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by:
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Ryo Kodama authored
This patch adds PWM clock for PWM. Signed-off-by:
Ryo Kodama <ryo.kodama.vz@renesas.com> Signed-off-by:
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Kazuya Mizuguchi authored
This patch adds HS-USB-IF clock for R8A7796 SoC. Signed-off-by:
Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by:
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Kazuya Mizuguchi authored
This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC. Signed-off-by: -
Kazuya Mizuguchi authored
This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00, CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1) clocks for R8A7796 SoC. Signed-off-by: -
Kazuya Mizuguchi authored
This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796 SoC. Signed-off-by: -
Hiromitsu Yamasaki authored
This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by:Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by:
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