1. 13 Jul, 2007 40 commits
    • Thomas Gleixner's avatar
      CFS: Fix missing digit off in wmult table · 4fd88517
      Thomas Gleixner authored
      Roman Zippel noticed another inconsistency of the wmult table.
      
      wmult[16] has a missing digit.
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      4fd88517
    • Linus Torvalds's avatar
      Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq · af09f1e4
      Linus Torvalds authored
      * master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq:
        [CPUFREQ] Fix typos in powernow-k8 printk's.
        [CPUFREQ] Restore previously used governor on a hot-replugged CPU
        [CPUFREQ] bugfix cpufreq in combination with performance governor
        [CPUFREQ] powernow-k8 compile fix.
        [CPUFREQ] the overdue removal of X86_SPEEDSTEP_CENTRINO_ACPI
        [CPUFREQ] Longhaul - Option to disable ACPI C3 support
      
      Fixed up arch/i386/kernel/cpu/cpufreq/powernow-k8.c due to revert that
      got fixed differently in the cpufreq branch.
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      af09f1e4
    • Linus Torvalds's avatar
      Merge branch 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop · e030dbf9
      Linus Torvalds authored
      * 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop: (28 commits)
        ioatdma: add the unisys "i/oat" pci vendor/device id
        ARM: Add drivers/dma to arch/arm/Kconfig
        iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver
        iop13xx: surface the iop13xx adma units to the iop-adma driver
        dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines
        md: remove raid5 compute_block and compute_parity5
        md: handle_stripe5 - request io processing in raid5_run_ops
        md: handle_stripe5 - add request/completion logic for async expand ops
        md: handle_stripe5 - add request/completion logic for async read ops
        md: handle_stripe5 - add request/completion logic for async check ops
        md: handle_stripe5 - add request/completion logic for async compute ops
        md: handle_stripe5 - add request/completion logic for async write ops
        md: common infrastructure for running operations with raid5_run_ops
        md: raid5_run_ops - run stripe operations outside sh->lock
        raid5: replace custom debug PRINTKs with standard pr_debug
        raid5: refactor handle_stripe5 and handle_stripe6 (v3)
        async_tx: add the async_tx api
        xor: make 'xor_blocks' a library routine for use with async_tx
        dmaengine: make clients responsible for managing channels
        dmaengine: refactor dmaengine around dma_async_tx_descriptor
        ...
      e030dbf9
    • Linus Torvalds's avatar
      Merge branch 'splice-2.6.23' of git://git.kernel.dk/data/git/linux-2.6-block · 12a22960
      Linus Torvalds authored
      * 'splice-2.6.23' of git://git.kernel.dk/data/git/linux-2.6-block:
        splice: fix offset mangling with direct splicing (sendfile)
        security: revalidate rw permissions for sys_splice and sys_vmsplice
        relay: fixup kerneldoc comment
        relay: fix bogus cast in subbuf_splice_actor()
      12a22960
    • Linus Torvalds's avatar
      Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus · 31c4ab43
      Linus Torvalds authored
      * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
        [MIPS] Workaround for a sparse warning in include/asm-mips/mach-tx4927/ioremap.h
        [MIPS] Make show_code static and add __user tag
        [MIPS] Workaround for a sparse warning in include/asm-mips/compat.h
        [MIPS] Add some __user tags
        [MIPS] math-emu minor cleanup
        [MIPS] Kill CONFIG_TX4927BUG_WORKAROUND
        [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_FB_XPERT98
        [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_SRC_CLK
        [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_USE32K
        [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1XXX_PSC_SPI
        [CHAR] Delete leftovers of old Alchemy UART driver
      31c4ab43
    • Linus Torvalds's avatar
      Revert "[CPUFREQ] powernow-k8: clarify number of cores." · 8b69ad0e
      Linus Torvalds authored
      This reverts commit 904f7a3f.
      
      As noted by Peter Anvin:
      
        "It causes build failures on i386.
      
         Yet another case of unnecessary divergence between i386 and x86-64
         I'm afraid..."
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      8b69ad0e
    • Linus Torvalds's avatar
      Merge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched · aba2da66
      Linus Torvalds authored
      * git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched:
        [PATCH] sched: small topology.h cleanup
        [PATCH] sched: fix show_task()/show_tasks() output
        [PATCH] sched: remove stale version info from kernel/sched_debug.c
        [PATCH] sched: allow larger granularity
        [PATCH] sched: fix prio_to_wmult[] for nice 1
      
      [ I re-did the commits to get rid of some bogus merge commit that
        Ingo had. - Linus ]
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      aba2da66
    • Ingo Molnar's avatar
      [PATCH] sched: small topology.h cleanup · f787a503
      Ingo Molnar authored
      trivial cleanup: LOCAL_DISTANCE and REMOTE_DISTANCE are only used in
      topology.h and inside an #ifndef section - limit their existence to
      that #ifndef.
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      f787a503
    • Ingo Molnar's avatar
      [PATCH] sched: fix show_task()/show_tasks() output · 4bd77321
      Ingo Molnar authored
      fix show_task()/show_tasks() output:
      
      - there's no sibling info anymore
      
      - the fields were not aligned properly with the description
      
      - get rid of the lazy-TLB output: it's been quite some time since
        we last had a bug there, and when we had a bug it wasnt helped a
        bit by this debug output.
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      4bd77321
    • Ingo Molnar's avatar
      [PATCH] sched: remove stale version info from kernel/sched_debug.c · 45f384a6
      Ingo Molnar authored
      kernel/sched_debug.c referred to CFS -v20, but there's no CFS versioning
      needed within the upstream kernel.
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      45f384a6
    • Ingo Molnar's avatar
      [PATCH] sched: allow larger granularity · a5968df8
      Ingo Molnar authored
      Allow granularity up to 100 msecs, instead of 10 msecs.
      (needed on larger boxes)
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      a5968df8
    • Mike Galbraith's avatar
      [PATCH] sched: fix prio_to_wmult[] for nice 1 · e127031f
      Mike Galbraith authored
      There's a typo in the values in prio_to_wmult[] for nice level 1.  While
      it did not cause bad CPU distribution, but caused more rescheduling
      between nice-0 and nice-1 tasks than necessary.
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      e127031f
    • Atsushi Nemoto's avatar
      [MIPS] Workaround for a sparse warning in include/asm-mips/mach-tx4927/ioremap.h · f24ae12b
      Atsushi Nemoto authored
      include2/asm/mach-tx49xx/ioremap.h:39:52: warning: cast truncates bits from constant value (fff000000 becomes ff000000)
      Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f24ae12b
    • Atsushi Nemoto's avatar
      e1bb8289
    • Atsushi Nemoto's avatar
      [MIPS] Workaround for a sparse warning in include/asm-mips/compat.h · 01bebc66
      Atsushi Nemoto authored
      Cast to a __user pointer via "unsigned long" to get rid of this warning:
      
      include2/asm/compat.h:135:10: warning: cast adds address space to expression (<asn:1>)
      Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      01bebc66
    • Atsushi Nemoto's avatar
      [MIPS] Add some __user tags · 5e0373b8
      Atsushi Nemoto authored
      Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5e0373b8
    • Atsushi Nemoto's avatar
      [MIPS] math-emu minor cleanup · e70dfc10
      Atsushi Nemoto authored
      Declaring emulpc and contpc as "unsigned long" can get rid of some casts.
      This also get rid of some sparse warnings.
      Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e70dfc10
    • Atsushi Nemoto's avatar
      [MIPS] Kill CONFIG_TX4927BUG_WORKAROUND · e50e1c74
      Atsushi Nemoto authored
      Kill workarounds for very early chip (perhaps pre-TX4927A).
      Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e50e1c74
    • Ralf Baechle's avatar
      [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_FB_XPERT98 · b58f4b7a
      Ralf Baechle authored
      Noticed by Robert P. J. Day (rpjday@mindspring.com).
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b58f4b7a
    • Ralf Baechle's avatar
      [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_SRC_CLK · 85a882bc
      Ralf Baechle authored
      Noticed by Robert P. J. Day (rpjday@mindspring.com).
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      85a882bc
    • Ralf Baechle's avatar
      [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_USE32K · 8f597aca
      Ralf Baechle authored
      Noticed by Robert P. J. Day (rpjday@mindspring.com).
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      8f597aca
    • Ralf Baechle's avatar
      [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1XXX_PSC_SPI · 6fec2e17
      Ralf Baechle authored
      Noticed by Robert P. J. Day (rpjday@mindspring.com).
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6fec2e17
    • Ralf Baechle's avatar
      33f60da0
    • Dan Williams's avatar
      ioatdma: add the unisys "i/oat" pci vendor/device id · 3039f073
      Dan Williams authored
      Cc: John Magolan <john.magolan@unisys.com>
      Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      3039f073
    • Dan Williams's avatar
      ARM: Add drivers/dma to arch/arm/Kconfig · 5816815f
      Dan Williams authored
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      5816815f
    • Dan Williams's avatar
      iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver · 2492c845
      Dan Williams authored
      Adds the platform device definitions and the architecture specific support
      routines (i.e. register initialization and descriptor formats) for the
      iop-adma driver.
      
      Changelog:
      * add support for > 1k zero sum buffer sizes
      * added dma/aau platform devices to iq80321 and iq80332 setup
      * fixed the calculation in iop_desc_is_aligned
      * support xor buffer sizes larger than 16MB
      * fix places where software descriptors are assumed to be contiguous, only
        hardware descriptors are contiguous for up to a PAGE_SIZE buffer size
      * convert to async_tx
      * add interrupt support
      * add platform devices for 80219 boards
      * do not call platform register macros in driver code
      * remove switch() statements for compatible register offsets/layouts
      * change over to bitmap based capabilities
      * remove unnecessary ARM assembly statement
      * checkpatch.pl fixes
      * gpl v2 only correction
      * phys move to dma_async_tx_descriptor
      
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      2492c845
    • Dan Williams's avatar
      iop13xx: surface the iop13xx adma units to the iop-adma driver · 39a8d7d1
      Dan Williams authored
      Adds the platform device definitions and the architecture specific
      support routines (i.e. register initialization and descriptor formats) for the
      iop-adma driver.
      
      Changelog:
      * added 'descriptor pool size' to the platform data
      * add base support for buffer sizes larger than 16MB (hw max)
      * build error fix from Kirill A. Shutemov
      * rebase for async_tx changes
      * add interrupt support
      * do not call platform register macros in driver code
      * remove unnecessary ARM assembly statement
      * checkpatch.pl fixes
      * gpl v2 only correction
      
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      39a8d7d1
    • Dan Williams's avatar
      dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines · c2110923
      Dan Williams authored
      The Intel(R) IOP series of i/o processors integrate an Xscale core with
      raid acceleration engines.  The capabilities per platform are:
      
      iop219:
       (2) copy engines
      iop321:
       (2) copy engines
       (1) xor and block fill engine
      iop33x:
       (2) copy and crc32c engines
       (1) xor, xor zero sum, pq, pq zero sum, and block fill engine
      iop34x (iop13xx):
       (2) copy, crc32c, xor, xor zero sum, and block fill engines
       (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine
      
      The driver supports the features of the async_tx api:
      * asynchronous notification of operation completion
      * implicit (interupt triggered) handling of inter-channel transaction
        dependencies
      
      The driver adapts to the platform it is running by two methods.
      1/ #include <asm/arch/adma.h> which defines the hardware specific
         iop_chan_* and iop_desc_* routines as a series of static inline
         functions
      2/ The private platform data attached to the platform_device defines the
         capabilities of the channels
      
      20070626: Callbacks are run in a tasklet.  Given the recent discussion on
      LKML about killing tasklets in favor of workqueues I did a quick conversion
      of the driver.  Raid5 resync performance dropped from 50MB/s to 30MB/s, so
      the tasklet implementation remains until a generic softirq interface is
      available.
      
      Changelog:
      * fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few
      slots to be requested eventually leading to data corruption
      * enabled the slot allocation routine to attempt to free slots before
      returning -ENOMEM
      * switched the cleanup routine to solely use the software chain and the
      status register to determine if a descriptor is complete.  This is
      necessary to support other IOP engines that do not have status writeback
      capability
      * make the driver iop generic
      * modified the allocation routines to understand allocating a group of
      slots for a single operation
      * added a null xor initialization operation for the xor only channel on
      iop3xx
      * support xor operations on buffers larger than the hardware maximum
      * split the do_* routines into separate prep, src/dest set, submit stages
      * added async_tx support (dependent operations initiation at cleanup time)
      * simplified group handling
      * added interrupt support (callbacks via tasklets)
      * brought the pending depth inline with ioat (i.e. 4 descriptors)
      * drop dma mapping methods, suggested by Chris Leech
      * don't use inline in C files, Adrian Bunk
      * remove static tasklet declarations
      * make iop_adma_alloc_slots easier to read and remove chances for a
        corrupted descriptor chain
      * fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt
      * convert capabilities over to dma_cap_mask_t
      * fixup sparse warnings
      * add descriptor flush before iop_chan_enable
      * checkpatch.pl fixes
      * gpl v2 only correction
      * move set_src, set_dest, submit to async_tx methods
      * move group_list and phys to async_tx
      
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      c2110923
    • Dan Williams's avatar
      md: remove raid5 compute_block and compute_parity5 · f6dff381
      Dan Williams authored
      replaced by raid5_run_ops
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      f6dff381
    • Dan Williams's avatar
      md: handle_stripe5 - request io processing in raid5_run_ops · 830ea016
      Dan Williams authored
      I/O submission requests were already handled outside of the stripe lock in
      handle_stripe.  Now that handle_stripe is only tasked with finding work,
      this logic belongs in raid5_run_ops.
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      830ea016
    • Dan Williams's avatar
      md: handle_stripe5 - add request/completion logic for async expand ops · f0a50d37
      Dan Williams authored
      When a stripe is being expanded bulk copying takes place to move the data
      from the old stripe to the new.  Since raid5_run_ops only operates on one
      stripe at a time these bulk copies are handled in-line under the stripe
      lock.  In the dma offload case we poll for the completion of the operation.
      
      After the data has been copied into the new stripe the parity needs to be
      recalculated across the new disks.  We reuse the existing postxor
      functionality to carry out this calculation.  By setting STRIPE_OP_POSTXOR
      without setting STRIPE_OP_BIODRAIN the completion path in handle stripe
      can differentiate expand operations from normal write operations.
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      f0a50d37
    • Dan Williams's avatar
      md: handle_stripe5 - add request/completion logic for async read ops · b5e98d65
      Dan Williams authored
      When a read bio is attached to the stripe and the corresponding block is
      marked R5_UPTODATE, then a read (biofill) operation is scheduled to copy
      the data from the stripe cache to the bio buffer.  handle_stripe flags the
      blocks to be operated on with the R5_Wantfill flag.  If new read requests
      arrive while raid5_run_ops is running they will not be handled until
      handle_stripe is scheduled to run again.
      
      Changelog:
      * cleanup to_read and to_fill accounting
      * do not fail reads that have reached the cache
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      b5e98d65
    • Dan Williams's avatar
      md: handle_stripe5 - add request/completion logic for async check ops · e89f8962
      Dan Williams authored
      Check operations are scheduled when the array is being resynced or an
      explicit 'check/repair' command was sent to the array.  Previously check
      operations would destroy the parity block in the cache such that even if
      parity turned out to be correct the parity block would be marked
      !R5_UPTODATE at the completion of the check.  When the operation can be
      carried out by a dma engine the assumption is that it can check parity as a
      read-only operation.  If raid5_run_ops notices that the check was handled
      by hardware it will preserve the R5_UPTODATE status of the parity disk.
      
      When a check operation determines that the parity needs to be repaired we
      reuse the existing compute block infrastructure to carry out the operation.
      Repair operations imply an immediate write back of the data, so to
      differentiate a repair from a normal compute operation the
      STRIPE_OP_MOD_REPAIR_PD flag is added.
      
      Changelog:
      * remove test_and_set/test_and_clear BUG_ONs, Neil Brown
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      e89f8962
    • Dan Williams's avatar
      md: handle_stripe5 - add request/completion logic for async compute ops · f38e1219
      Dan Williams authored
      handle_stripe will compute a block when a backing disk has failed, or when
      it determines it can save a disk read by computing the block from all the
      other up-to-date blocks.
      
      Previously a block would be computed under the lock and subsequent logic in
      handle_stripe could use the newly up-to-date block.  With the raid5_run_ops
      implementation the compute operation is carried out a later time outside
      the lock.  To preserve the old functionality we take advantage of the
      dependency chain feature of async_tx to flag the block as R5_Wantcompute
      and then let other parts of handle_stripe operate on the block as if it
      were up-to-date.  raid5_run_ops guarantees that the block will be ready
      before it is used in another operation.
      
      However, this only works in cases where the compute and the dependent
      operation are scheduled at the same time.  If a previous call to
      handle_stripe sets the R5_Wantcompute flag there is no facility to pass the
      async_tx dependency chain across successive calls to raid5_run_ops.  The
      req_compute variable protects against this case.
      
      Changelog:
      * remove the req_compute BUG_ON
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      f38e1219
    • Dan Williams's avatar
      md: handle_stripe5 - add request/completion logic for async write ops · e33129d8
      Dan Williams authored
      After handle_stripe5 decides whether it wants to perform a
      read-modify-write, or a reconstruct write it calls
      handle_write_operations5.  A read-modify-write operation will perform an
      xor subtraction of the blocks marked with the R5_Wantprexor flag, copy the
      new data into the stripe (biodrain) and perform a postxor operation across
      all up-to-date blocks to generate the new parity.  A reconstruct write is run
      when all blocks are already up-to-date in the cache so all that is needed
      is a biodrain and postxor.
      
      On the completion path STRIPE_OP_PREXOR will be set if the operation was a
      read-modify-write.  The STRIPE_OP_BIODRAIN flag is used in the completion
      path to differentiate write-initiated postxor operations versus
      expansion-initiated postxor operations.  Completion of a write triggers i/o
      to the drives.
      
      Changelog:
      * make the 'rcw' parameter to handle_write_operations5 a simple flag, Neil Brown
      * remove test_and_set/test_and_clear BUG_ONs, Neil Brown
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      e33129d8
    • Dan Williams's avatar
      md: common infrastructure for running operations with raid5_run_ops · d84e0f10
      Dan Williams authored
      All the handle_stripe operations that are to be transitioned to use
      raid5_run_ops need a method to coherently gather work under the stripe-lock
      and hand that work off to raid5_run_ops.  The 'get_stripe_work' routine
      runs under the lock to read all the bits in sh->ops.pending that do not
      have the corresponding bit set in sh->ops.ack.  This modified 'pending'
      bitmap is then passed to raid5_run_ops for processing.
      
      The transition from 'ack' to 'completion' does not need similar protection
      as the existing release_stripe infrastructure will guarantee that
      handle_stripe will run again after a completion bit is set, and
      handle_stripe can tolerate a sh->ops.completed bit being set while the lock
      is held.
      
      A call to async_tx_issue_pending_all() is added to raid5d to kick the
      offload engines once all pending stripe operations work has been submitted.
      This enables batching of the submission and completion of operations.
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      d84e0f10
    • Dan Williams's avatar
      md: raid5_run_ops - run stripe operations outside sh->lock · 91c00924
      Dan Williams authored
      When the raid acceleration work was proposed, Neil laid out the following
      attack plan:
      
      1/ move the xor and copy operations outside spin_lock(&sh->lock)
      2/ find/implement an asynchronous offload api
      
      The raid5_run_ops routine uses the asynchronous offload api (async_tx) and
      the stripe_operations member of a stripe_head to carry out xor+copy
      operations asynchronously, outside the lock.
      
      To perform operations outside the lock a new set of state flags is needed
      to track new requests, in-flight requests, and completed requests.  In this
      new model handle_stripe is tasked with scanning the stripe_head for work,
      updating the stripe_operations structure, and finally dropping the lock and
      calling raid5_run_ops for processing.  The following flags outline the
      requests that handle_stripe can make of raid5_run_ops:
      
      STRIPE_OP_BIOFILL
       - copy data into request buffers to satisfy a read request
      STRIPE_OP_COMPUTE_BLK
       - generate a missing block in the cache from the other blocks
      STRIPE_OP_PREXOR
       - subtract existing data as part of the read-modify-write process
      STRIPE_OP_BIODRAIN
       - copy data out of request buffers to satisfy a write request
      STRIPE_OP_POSTXOR
       - recalculate parity for new data that has entered the cache
      STRIPE_OP_CHECK
       - verify that the parity is correct
      STRIPE_OP_IO
       - submit i/o to the member disks (note this was already performed outside
         the stripe lock, but it made sense to add it as an operation type
      
      The flow is:
      1/ handle_stripe sets STRIPE_OP_* in sh->ops.pending
      2/ raid5_run_ops reads sh->ops.pending, sets sh->ops.ack, and submits the
         operation to the async_tx api
      3/ async_tx triggers the completion callback routine to set
         sh->ops.complete and release the stripe
      4/ handle_stripe runs again to finish the operation and optionally submit
         new operations that were previously blocked
      
      Note this patch just defines raid5_run_ops, subsequent commits (one per
      major operation type) modify handle_stripe to take advantage of this
      routine.
      
      Changelog:
      * removed ops_complete_biodrain in favor of ops_complete_postxor and
        ops_complete_write.
      * removed the raid5_run_ops workqueue
      * call bi_end_io for reads in ops_complete_biofill, saves a call to
        handle_stripe
      * explicitly handle the 2-disk raid5 case (xor becomes memcpy), Neil Brown
      * fix race between async engines and bi_end_io call for reads, Neil Brown
      * remove unnecessary spin_lock from ops_complete_biofill
      * remove test_and_set/test_and_clear BUG_ONs, Neil Brown
      * remove explicit interrupt handling for channel switching, this feature
        was absorbed (i.e. it is now implicit) by the async_tx api
      * use return_io in ops_complete_biofill
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      91c00924
    • Dan Williams's avatar
      raid5: replace custom debug PRINTKs with standard pr_debug · 45b4233c
      Dan Williams authored
      Replaces PRINTK with pr_debug, and kills the RAID5_DEBUG definition in
      favor of the global DEBUG definition.  To get local debug messages just add
      '#define DEBUG' to the top of the file.
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      45b4233c
    • Dan Williams's avatar
      raid5: refactor handle_stripe5 and handle_stripe6 (v3) · a4456856
      Dan Williams authored
      handle_stripe5 and handle_stripe6 have very deep logic paths handling the
      various states of a stripe_head.  By introducing the 'stripe_head_state'
      and 'r6_state' objects, large portions of the logic can be moved to
      sub-routines.
      
      'struct stripe_head_state' consumes all of the automatic variables that previously
      stood alone in handle_stripe5,6.  'struct r6_state' contains the handle_stripe6
      specific variables like p_failed and q_failed.
      
      One of the nice side effects of the 'stripe_head_state' change is that it
      allows for further reductions in code duplication between raid5 and raid6.
      The following new routines are shared between raid5 and raid6:
      
      	handle_completed_write_requests
      	handle_requests_to_failed_array
      	handle_stripe_expansion
      
      Changes:
      * v2: fixed 'conf->raid_disk-1' for the raid6 'handle_stripe_expansion' path
      * v3: removed the unused 'dirty' field from struct stripe_head_state
      * v3: coalesced open coded bi_end_io routines into return_io()
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      a4456856
    • Dan Williams's avatar
      async_tx: add the async_tx api · 9bc89cd8
      Dan Williams authored
      The async_tx api provides methods for describing a chain of asynchronous
      bulk memory transfers/transforms with support for inter-transactional
      dependencies.  It is implemented as a dmaengine client that smooths over
      the details of different hardware offload engine implementations.  Code
      that is written to the api can optimize for asynchronous operation and the
      api will fit the chain of operations to the available offload resources. 
       
      	I imagine that any piece of ADMA hardware would register with the
      	'async_*' subsystem, and a call to async_X would be routed as
      	appropriate, or be run in-line. - Neil Brown
      
      async_tx exploits the capabilities of struct dma_async_tx_descriptor to
      provide an api of the following general format:
      
      struct dma_async_tx_descriptor *
      async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
      			dma_async_tx_callback cb_fn, void *cb_param)
      {
      	struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
      	struct dma_device *device = chan ? chan->device : NULL;
      	int int_en = cb_fn ? 1 : 0;
      	struct dma_async_tx_descriptor *tx = device ?
      		device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
      
      	if (tx) { /* run <operation> asynchronously */
      		...
      		tx->tx_set_dest(addr, tx, index);
      		...
      		tx->tx_set_src(addr, tx, index);
      		...
      		async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
      	} else { /* run <operation> synchronously */
      		...
      		<operation>
      		...
      		async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
      	}
      
      	return tx;
      }
      
      async_tx_find_channel() returns a capable channel from its pool.  The
      channel pool is organized as a per-cpu array of channel pointers.  The
      async_tx_rebalance() routine is tasked with managing these arrays.  In the
      uniprocessor case async_tx_rebalance() tries to spread responsibility
      evenly over channels of similar capabilities.  For example if there are two
      copy+xor channels, one will handle copy operations and the other will
      handle xor.  In the SMP case async_tx_rebalance() attempts to spread the
      operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
      channel0 while cpu1 gets copy channel 1 and xor channel 1.  When a
      dependency is specified async_tx_find_channel defaults to keeping the
      operation on the same channel.  A xor->copy->xor chain will stay on one
      channel if it supports both operation types, otherwise the transaction will
      transition between a copy and a xor resource.
      
      Currently the raid5 implementation in the MD raid456 driver has been
      converted to the async_tx api.  A driver for the offload engines on the
      Intel Xscale series of I/O processors, iop-adma, is provided in a later
      commit.  With the iop-adma driver and async_tx, raid456 is able to offload
      copy, xor, and xor-zero-sum operations to hardware engines.
       
      On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
      improvement) and sequential reads to a degraded array (40 - 55%
      improvement).  For the other cases performance was roughly equal, +/- a few
      percentage points.  On a x86-smp platform the performance of the async_tx
      implementation (in synchronous mode) was also +/- a few percentage points
      of the original implementation.  According to 'top' on iop342 CPU
      utilization drops from ~50% to ~15% during a 'resync' while the speed
      according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
       
      The tiobench command line used for testing was: tiobench --size 2048
      --block 4096 --block 131072 --dir /mnt/raid --numruns 5
      * iop342 had 1GB of memory available
      
      Details:
      * if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
        async_tx_find_channel a static inline routine that always returns NULL
      * when a callback is specified for a given transaction an interrupt will
        fire at operation completion time and the callback will occur in a
        tasklet.  if the the channel does not support interrupts then a live
        polling wait will be performed
      * the api is written as a dmaengine client that requests all available
        channels
      * In support of dependencies the api implicitly schedules channel-switch
        interrupts.  The interrupt triggers the cleanup tasklet which causes
        pending operations to be scheduled on the next channel
      * Xor engines treat an xor destination address differently than a software
        xor routine.  To the software routine the destination address is an implied
        source, whereas engines treat it as a write-only destination.  This patch
        modifies the xor_blocks routine to take a an explicit destination address
        to mirror the hardware.
      
      Changelog:
      * fixed a leftover debug print
      * don't allow callbacks in async_interrupt_cond
      * fixed xor_block changes
      * fixed usage of ASYNC_TX_XOR_DROP_DEST
      * drop dma mapping methods, suggested by Chris Leech
      * printk warning fixups from Andrew Morton
      * don't use inline in C files, Adrian Bunk
      * select the API when MD is enabled
      * BUG_ON xor source counts <= 1
      * implicitly handle hardware concerns like channel switching and
        interrupts, Neil Brown
      * remove the per operation type list, and distribute operation capabilities
        evenly amongst the available channels
      * simplify async_tx_find_channel to optimize the fast path
      * introduce the channel_table_initialized flag to prevent early calls to
        the api
      * reorganize the code to mimic crypto
      * include mm.h as not all archs include it in dma-mapping.h
      * make the Kconfig options non-user visible, Adrian Bunk
      * move async_tx under crypto since it is meant as 'core' functionality, and
        the two may share algorithms in the future
      * move large inline functions into c files
      * checkpatch.pl fixes
      * gpl v2 only correction
      
      Cc: Herbert Xu <herbert@gondor.apana.org.au>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Acked-By: default avatarNeilBrown <neilb@suse.de>
      9bc89cd8