- 25 May, 2017 2 commits
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Hawking Zhang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Hawking Zhang authored
Signed-off-by:
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- 24 May, 2017 38 commits
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Lyude authored
Same as the previous patch, but for pageflipping now. This also lets us clear up the copy paste for vblank/vline IRQs. Changes since v1: - Preserve the order all registers are written back Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Lyude <lyude@redhat.com> Signed-off-by:
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Lyude authored
Same as the previous patch, but now for handling HDMI audio interrupts. Changes since v1: - Preserve the order we write back all registers Acked-by:
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Lyude authored
The current code here is really, really bad. A huge amount of it looks to be copy pasted, it has some weird hatred of arrays and code sharing, switch cases everywhere for things that really don't need them, and it makes the file seem immensely more complex then it actually is. This is a pain for maintanence, and is vulnerable to more weird irq handling bugs. So, let's start cleaning this up a bit. Modify all of the IRQ handlers for evergreen/si so that they just use for loops. As well, we add a helper function radeon_irq_kms_set_irq_n_enabled(), whose purpose is just to update the state of registers that enable/disable interrupts while printing any changes to the set of enabled interrupts to the kernel log. Note in this commit, since vblank/vline irq acking is intertwined with page flip irq acking, we can't cut out all of the copy paste in evergreen/si_irq_ack() just yet. Changes since v1: - Preserve order we write back all registers Acked-by:
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Alex Deucher authored
KIQ is the Kernel Interface Queue for managing the MEC. Rather than setting up rings via direct MMIO of ring registers, the rings are configured via special packets sent to the KIQ. The allows the MEC to better manage shared resources and certain power events. It also reduces the code paths in the driver to support and is required for MEC powergating. v2: drop gfx_v9_0_cp_compute_fini() as well v3: rebase on latest changes derived from gfx8, add unmap queues on hw_fini v4: fix copy/paste typo in error message (Rex) Acked-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Alex Deucher authored
No need to reset the wptr and clear the rings. The UNMAP_QUEUES packet writes the current MQD state back the MQD on suspend, so there is no need to reset it as well. v2: fix from gfx8 (Rex) Acked-by:
monk liu <monk.liu@amd.com> Signed-off-by:
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Alex Deucher authored
As the KCQ setup. This way we only have to wait once for the entire MEC. Acked-by:
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Alex Deucher authored
Rather than waiting for each queue. Acked-by:
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Alex Deucher authored
One for KIQ and one for the KCQ. This simplifies the logic and allows for future optimizations. Acked-by:
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Alex Deucher authored
It's stored in LE format. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
Sets floors for various clocks depending on current requirements. Signed-off-by:
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Rex Zhu authored
Add the new clock type to the gfx arbitor so we can determine the proper clock floors for it. Signed-off-by:
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Rex Zhu authored
New clock type on RV. Signed-off-by:
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Rex Zhu authored
Print the failed msg when it fails. Signed-off-by:
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Rex Zhu authored
Add additional smu messages. Signed-off-by:
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Rex Zhu authored
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Marek Olšák authored
v2: bump the DRM version Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Tom St Denis authored
If you initiate a read that is out of the VRAM address space return ENXIO instead of 0. Reads that begin below that point will read upto the VRAM limit as before. Cc: stable@vger.kernel.org Signed-off-by:
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Felix Kuehling authored
If AMDGPU supports CIK, add a module parameter to control CIK support in radeon. It's off by default in radeon, while it will be on by default in AMDGPU. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Drop the function gmc_v6_0_init_compute_vmid() since it wasn't implemented and commented out. Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
Clean up coding style in gfx_v6_0_write_harvested_raster_configs() Signed-off-by:
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Tom St Denis authored
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Christian König authored
That line got missed during the merge. v2: fix vcn_v1_0_enc_ring_emit_vm_flush as well Signed-off-by:
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Christian König authored
That GFX9 needs a PDE in the registers is entirely GFX9 specific. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
512 is enough for one PD entry on Vega10. Signed-off-by:
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Flora Cui authored
partial revert commit <6971d3d> - drm/amdgpu: cleanup logic in amdgpu_vm_flush Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
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Yintian Tao authored
If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
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Christian König authored
VM is mandatory for all hw amdgpu supports. So remove the leftovers to make it optionally. Signed-off-by:
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Chunming Zhou authored
The fence in dep_sync cannot be optimized. Signed-off-by:
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Ken Wang authored
Update gfx9 golden settings. Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Acked-by:
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Chunming Zhou authored
If the vm is guilty of a GPU reset, skips all its jobs. Signed-off-by:
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Chunming Zhou authored
below ioctl will return -ENODEV: amdgpu_cs_ioctl amdgpu_cs_wait_ioctl amdgpu_cs_wait_fences_ioctl amdgpu_gem_va_ioctl amdgpu_info_ioctl v2: only for map and replace cases in amdgpu_gem_va_ioctl Signed-off-by:
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Chunming Zhou authored
backup first 64 byte of gart table as reset magic, check if magic is same after gpu hw reset. v2: use memcmp instead of manual innovation. Signed-off-by:
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Felix Kuehling authored
Clock index 0 is a valid index that is needed to restore the default graphics power profile. Use ~0 to indicate a failure to find a clock index. This fixes the clocks getting stuck in the compute power profile after running a compute application on Vega10. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Alex Deucher authored
Add support for parsing the gpu info table on raven. This is required to get the gpu config data for raven. Signed-off-by:
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