1. 18 Apr, 2013 17 commits
  2. 08 Apr, 2013 4 commits
  3. 06 Apr, 2013 3 commits
  4. 05 Apr, 2013 6 commits
  5. 03 Apr, 2013 10 commits
    • Daniel Vetter's avatar
      drm/i915: create pipe_config->dpll for clock state · f47709a9
      Daniel Vetter authored
      Clock computations and handling are highly encoder specific, both in
      the optimal clock selection and also in which clocks to use and when
      sharing of clocks is possible.
      
      So the best place to do this is somewhere in the encoders, with a
      generic fallback for those encoders without special needs. To facility
      this, add a pipe_config->clocks_set boolean.
      
      This patch here is only prep work, it simply sets the computed clock
      values in pipe_config->dpll, and uses that data in the hw clock
      setting functions.
      
      Haswell code isn't touched, simply because Haswell clocks work much
      different and need their own infrastructure (with probably a
      Haswell-specific config->ddi_clock substruct).
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      f47709a9
    • Daniel Vetter's avatar
      drm/i915: hw readout support for ->has_pch_encoders · 88adfff1
      Daniel Vetter authored
      Now we can ditch the checks in the Haswell disable code.
      
      v2: add support for Haswell
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      88adfff1
    • Daniel Vetter's avatar
      drm/i915: add hw state readout/checking for pipe_config · 0e8ffe1b
      Daniel Vetter authored
      We need to be able to read out the hw state code for a bunch
      of reasons:
      - Correctly disabling boot-up/resume state.
      - Pure paranoia.
      
      Since not all of the pipe configuration is e.g. relevant for
      fastboot (or at least we can allow some wiggle room in some
      parameters, like the clocks), we need to add a strict_checking
      parameter to intel_pipe_config_compare for fastboot.
      
      For now intel_pipe_config_compare should be fully paranoid and
      check everything that the hw state readout code supports. Which
      for this infrastructure code is nothing.
      
      I've gone a bit overboard with adding 3 get_pipe_config functions:
      The ilk version will differ with the next patch, so it's not too
      onerous.
      
      v2: Don't check the hw config if the pipe is off, since an enabled,
      but dpms off crtc will obviously have tons of difference with the hw
      state.
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      0e8ffe1b
    • Daniel Vetter's avatar
      drm/i915: rip out superflous is_dp&is_cpu_edp tracking · 8b47047b
      Daniel Vetter authored
      The only exception left is is_cpu_edp in the haswell modeset code.
      We need that to assign the cpu transcoder, but we might want to
      move that eventually into the encoder, too.
      
      \o/-by: Jesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      8b47047b
    • Daniel Vetter's avatar
      drm/i915: remove leaky eDP functions · 947978fa
      Daniel Vetter authored
      Jesse Barnes noticed in his review of my DP cleanup series that
      intel_edp_target_clock is now unused. Checking related code I've
      noticed that also intel_edp_link_config is long unused.
      
      Kill them both.
      
      Wrt leaky eDP functions used in the common crtc code, the only thing
      still left is intel_encoder_is_pch_edp. That one is just due to the
      massive confusion between eDP vs. DP and port A vs. port D. Crtc code
      should at most concern itself with the later, never with the former.
      
      But that's material for another patch series.
      
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      947978fa
    • Daniel Vetter's avatar
      drm/i915: track dp target_clock in pipe_config · df92b1e6
      Daniel Vetter authored
      We need it in the fdi m_n computation, which nicely kills almost
      all ugly special cases in there.
      
      It looks like we also need this to handle 12bpc hdmi correctly.
      
      Eventually it might be better to switch things around and put the
      target clock into adjusted_mode->clock and create a new pipe_config
      parameter for the port link clock.
      
      v2: Add a massive comment in the code to explain this mess.
      
      v3: s/dp_target_clock/pixel_target_clock in anticipation of the hdmi
      use-case.
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      df92b1e6
    • Daniel Vetter's avatar
      drm/i915: move dp_m_n computation to dp_encoder->compute_config · 03afc4a2
      Daniel Vetter authored
      We need a flag to designate dp encoders and the dp link m_n parameters
      in the pipe config for that. And now that the pipe bpp computations
      have been moved up and stored in the pipe config, too, we can do this
      without losing our sanity.
      
      v2: Rebased on top of Takashi Iwai's fix to (again) fix the target
      clock handling for eDP. Luckily the new code is sane enough and just
      does the right thing!
      
      v3: Move ->has_dp_encoder to this patch (Jesse).
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      03afc4a2
    • Daniel Vetter's avatar
      drm/i915: clear up the fdi/dp set_m_n confusion · 6cf86a5e
      Daniel Vetter authored
      There's a rather decent confusion going on around transcoder m_n
      values. So let's clarify:
      - All dp encoders need this, either on the pch transcoder if it's a
        pch port, or on the cpu transcoder/pipe if it's a cpu port.
      - fdi links need to have the right m_n values for the fdi link set in
        the cpu transcoder.
      
      To handle the pch vs transcoder stuff a bit better, extract transcoder
      set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder
      als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n
      registers are all at the same offset) can use it.
      
      Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs.
      edp works exactly the same as dp (since there's no pch dp any more),
      so use that as a check. And only set up the fdi m_n values if we
      really have a pch encoder present (which means we have a VGA encoder).
      
      On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch
      encoders. Now that dp_set_m_n handles all dp links (thanks to the
      pch encoder check), we can ditch the cpu_edp stuff from the
      fdi_set_m_n function.
      
      Since the dp_m_n values are not readily available, we need to
      carefully coax the edp values out of the encoder. Hence we can't (yet)
      kill this superflous complexity.
      
      v2: Rebase on top of the ivb fdi B/C check patch - we need to properly
      clear intel_crtc->fdi_lane, otherwise those checks will misfire.
      
      v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni.
      
      v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse).
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      6cf86a5e
    • Daniel Vetter's avatar
      Merge tag 'v3.9-rc5' into drm-intel-next-queued · ecb135a1
      Daniel Vetter authored
      Backmerge Linux 3.9-rc5 since I want to merge a few dp clock cleanups
      for -next, but they will conflict all over the place with
      
      commit 9d1a455b
      Author: Takashi Iwai <tiwai@suse.de>
      Date:   Mon Mar 18 11:25:36 2013 +0100
      
          drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n()
      
      from -fixes.
      
      Conflicts:
      	drivers/gpu/drm/i915/intel_dp.c: Simply adjacent lines changed.
      	drivers/gpu/drm/i915/intel_panel.c: A field rename in -next
      	conflicts with a bugfix in -fixes. Take the version from
      	-fixes and apply the rename.
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      ecb135a1
    • Daniel Vetter's avatar
      drm/i915: Fix sdvo connector get_hw_state function · bd6946e8
      Daniel Vetter authored
      The active output is only the currently selected one, which does not
      imply that it's actually enabled. Since we don't use the sdvo encoder
      side dpms support, we need to check whether the chip-side sdvo port is
      enabled instead.
      
      v2: Fix up Bugzilla links.
      
      v3: Simplify logic a bit (Chris).
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60138
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031
      Cc: Egbert Eich <eich@pdx.freedesktop.org>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Tested-by: Egbert Eich <eich@pdx.freedesktop.org> (v2)
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      bd6946e8