- 16 May, 2014 8 commits
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Valentin Longchamp authored
Besides our Kirkwood Reference design, there is another group of board on which the eth interface is not connected to a phy but to a switch for some board internal communication. For these designs, the memory also is raised to 256MB. The configuration of the switch is handled by an EEPROM or by the bootloader, but on the kirkwood side, the port is always configured as 1000 Mbits, full duplex. Signed-off-by:
Valentin Longchamp <valentin.longchamp@keymile.com> Link: https://lkml.kernel.org/r/1400230143-15620-4-git-send-email-valentin.longchamp@keymile.comAcked-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Valentin Longchamp authored
This file allows to factor the common parts between the various Keymile Kirkwood Designs. kirkwood-km_common configures the peripherals that are currently common to all our Kirkwood designs: PCIe, pinctrl, bitbang I2C, NAND Flash controller. The kirkwood-km_kirkwood file is then changed to include this common file. Signed-off-by:
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Valentin Longchamp authored
The 98DX4122 dtsi file lacks the defintion of the PCIe controller which is present on this SoC. The SATA phys must also be explicitely disabled since they are not present on this SoC. If they remain enabled, a hardlock occures when their clock gates are enabled. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
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Gregory CLEMENT authored
The Marvell Armada 375 SoCs contains two EHCI controllers. This commit adds the Device Tree description of these interfaces at the SoC level, and also enables the USB2 port on the Armada 375 DB platform. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1400149062-32661-18-git-send-email-gregory.clement@free-electrons.comSigned-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Gregory CLEMENT authored
The Marvell Armada 375 SoCs contain a xHCI controller. This commit adds the Device Tree description of this interfaces at the SoC level, and also enables the USB3 port on the Armada 375 DB platform. Signed-off-by:
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Gregory CLEMENT authored
The Marvell Armada 38x SoCs contains one EHCI controller. This commit adds the Device Tree description of this interface at the SoC level, and also enables the USB2 port on the Armada 385 DB platform. Signed-off-by:
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Gregory CLEMENT authored
The Marvell Armada 38x SoCs contains two xHCI controllers. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables the two USB3 ports on the Armada 385 DB platform and one USB3 port on the Armada 385 RD platform. Signed-off-by:
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Andrew Lunn authored
Create DTS files to describe the Marvell OpenRD boards. Signed-off-by:
Francois Lorrain <francois.lorrain@gmail.com> Acked-by:
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- 05 May, 2014 17 commits
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Andrew Lunn authored
Add device tree nodes to instantiate the audio drivers on the HP T5325 device. Signed-off-by:
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Andrew Lunn authored
The sound node is missing a #sound-dai-cells property. Add it, so that the sounds node can be used in combination with the simple-audio-card binding. Signed-off-by:
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Andrew Lunn authored
Instantiate the audio codec via a DT node. Signed-off-by:
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Sebastian Hesselbarth authored
Ethernet PHYs found on Globalscale Guruplug are connected by RGMII-ID. Set the corresponding phy-connection-type property accordingly. Signed-off-by:
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Sebastian Hesselbarth authored
Ethernet PHY compatible shall be "ethernet-phy-ieee802.3-c22" and "ethernet-phy-idAAAA.BBBB" if PHY OUI id is known. We know it for the PHY found on Guruplug, so set it accordingly. Signed-off-by:
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Sebastian Hesselbarth authored
Currently, the only 6282-based Kirkwood boards that use I2C1 are Openblocks A6/A7. Both use the same default I2C1 pinctrl setting from kirkwood-6282.dtsi. Move the pinctrl setting to the I2C1 node directly and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Signed-off-by:
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Sebastian Hesselbarth authored
There is only one valid pinctrl setting for I2C0 on Kirkwood. Now that we have the setting in the common SoC pinctrl, move it to the I2C0 controller node directly and remove it from the individual boards. While at it, also fix up status = "okay" to "ok" on one board's I2C0 node. Signed-off-by:
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Sebastian Hesselbarth authored
There is only one valid pinctrl setting for NAND on Kirkwood. Now that we have the setting in the common SoC pinctrl, move it to the NAND controller node directly and remove it from the individual boards. While at it, also fix up status = "okay" to "ok" on one board's NAND node. Signed-off-by:
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Sebastian Hesselbarth authored
Most Kirkwood boards use the default SPI0 pinctrl setting anyway. Add a default pinctrl setting to the toplevel SoC SPI0 node and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Currently, only T5325 is using a different setting and already overwrites the corresponding pinctrl node. Signed-off-by:
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Sebastian Hesselbarth authored
Most boards use the default UART0/1 pinctrl setting without RTS/CTS. Add the pinctrl setting to the toplevel SoC UART nodes and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Currently, both boards using a different UART pinctrl setting (Openblocks A6, A7) already overwrite the pinctrl node. While at it, also fix up some status = "ok" to "okay" and again whitespace issues on mplcec4 uart nodes. Signed-off-by:
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Sebastian Hesselbarth authored
On Kirkwood, there is only one valid pinctrl setting for GBE1. With a common SoC pinctrl node, we can now set it in the node instead of in each board file. Signed-off-by:
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Sebastian Hesselbarth authored
All SoCs have the same pinctrl setting for NAND, UART0/1, SPI, TWSI0, and GBE1. Move it to the common pinctrl node that we now have. Signed-off-by:
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Sebastian Hesselbarth authored
All Kirkwood SoCs have their pinctrl registers at the same address. Instead of replaying the same reg property on each SoC, have the reg property set in the common SoC file already. This also allows us to move common pinctrl settings to this node later on. Signed-off-by:
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Sebastian Hesselbarth authored
To prepare pin-controller consolidation, first rename all pinctrl nodes to a more appropriate name regarding ePAPR recommended names. Signed-off-by:
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Sebastian Hesselbarth authored
UART devices found on Kirkwood SoCs derive their baudrate from TCLK. With proper clocks property in the SoCs serial node, boards do not need to overwrite it anymore. Remove the remaining clock-frequency property from all Kirkwood boards. Signed-off-by:
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Sebastian Hesselbarth authored
ePAPR allows to reference the device used for console output by stdout-path property. With node labels for Kirkwood UART0, now reference it on all Kirkwood boards that already have ttyS0 in their bootargs property. While at it, fix some whitespace issues on mplcec4's chosen node (there are more, but we only fix the chosen node now) Signed-off-by:
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Sebastian Hesselbarth authored
This adds missing node labels to Kirkwood common and SoC specific nodes to allow to reference them more easily. Signed-off-by:
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- 28 Apr, 2014 1 commit
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Ezequiel Garcia authored
This commit enables the thermal sensor found in Armada 380/385 SoCs. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398371004-15807-11-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by:
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- 26 Apr, 2014 5 commits
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Ezequiel Garcia authored
This commit enables the thermal sensor found in Armada 375 SoCs. Signed-off-by:
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Thomas Petazzoni authored
The Netgear RN2120 was not using the same strategy as the other Armada 370/375/38x/XP boards: it was using a 'clocks' property and not the 'clock-frequency' property in its UART controller Device Tree node. However, now that this clock reference is present at the SoC-level, there is no point in duplicating it at the board-level. Signed-off-by:
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Thomas Petazzoni authored
Now that the Armada 370/375/38x/XP SoC-level Device Tree files have the proper "clocks" property in their UART controllers node, it is no longer useful to have the clock-frequency property defined in the board-level Device Tree files. Therefore, this commit gets rid of all the useless 'clock-frequency' properties. Signed-off-by:
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Thomas Petazzoni authored
Back when the Armada 370 and Armada XP initial support was introduced, the only way to pass the clock frequency to the of_serial driver was through a clock-frequency Device Tree property. Thanks to 0bbeb3c3 ('of serial port driver - add clk_get_rate() support'), it is possible to use the standard 'clocks' DT property to reference the clock used for a particular UART controller. This clock is then used by the of_serial driver to retrieve the clock rate. This commit modifies the SoC-level Device Tree files of Armada 370, Armada XP, Armada 375 and Armada 38x to use this possibility. Since there is no gatable clock for the UART controllers, we simply reference the TCLK, which is the main SoC clock for the peripherals. Signed-off-by:
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Thomas Petazzoni authored
The Marvell Armada 38x processors contain two AHCI compatible interfaces. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables them on the Armada 385 DB platform, which allows access to both interfaces through SATA ports. Signed-off-by:
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- 25 Apr, 2014 1 commit
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Thomas Petazzoni authored
In commit "mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller", the sdhci-pxav3 driver has been extended to also be usable on Armada 38x platforms. Therefore, this commit adds the necessary Device Tree informations to declare this SDHCI interface in the Armada 38x SoC, and also in the Armada 385 Development Board. Signed-off-by:
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- 24 Apr, 2014 8 commits
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Thomas Petazzoni authored
This commit improves the Armada 38x Device Tree to add the CPU reset and PMSU Device Tree nodes as well as the declaration of the enabling method for the CPUs. These are needed to get SMP working on Armada 38x platforms. Signed-off-by:
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Gregory CLEMENT authored
Improve the Armada 375 Device Tree to add the CPU reset Device Tree node and declare the enabling method for CPUs, both of which are necessary to get SMP working. Signed-off-by:
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Thomas Petazzoni authored
This commit updates the Armada XP Device Trees (for the three variants of Armada XP) to declare the "enable-method" property for the CPUs, which helps operating systems find the appropriate logic to manage the CPUs, especially to boot secondary CPUs. Signed-off-by:
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Gregory CLEMENT authored
Following the introduction of the new PMSU Device Tree binding, as well as the separate CPU reset binding, this commit switches the Armada 370 and Armada XP Device Trees to use them. The PMSU node is moved from the Armada XP specific armada-xp.dtsi to the common Armada 370/XP armada-370-xp.dtsi because the PMSU is in fact available at the same location on both SOCs. The CPU reset node is then added on both Armada 370 and Armada XP, with a different compatible string. On Armada 370, the CPU reset driver is not really needed as Armada 370 is single core and the only use of the CPU reset driver is to boot secondary processors, but it still makes sense to have this CPU reset register described in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 38x. Signed-off-by:
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Thomas Petazzoni authored
This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 375. Signed-off-by:
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Ezequiel Garcia authored
Add the DT nodes to enable the watchdog support available on Armada 380/385 SoC. Reviewed-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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Ezequiel Garcia authored
Add the DT nodes to enable the watchdog support available on Armada 375 SoC. Reviewed-by:
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