1. 10 Jan, 2014 4 commits
    • Paulo Zanoni's avatar
      drm/i915: don't set modes for 2 connectors on the same encoder · 5a65f358
      Paulo Zanoni authored
      In some cases we have more than 1 connector associated to an encoder
      (e.g., SDVO, Haswell DP/HDMI) and we can only set a mode for one of
      these connectors. If we only allowed modesets for connected connectors
      we would never need this patch, but since we do allow modeset for
      disconnected connectors we may see user space trying to set modes on
      the two connectors attached to the same encoder, so we need to forbid
      that.
      
      This problem can be reproduced by running the following
      intel-gpu-tools test case:
        ./kms_setmode --run-subtest clone-exclusive-crtc
      
      Thanks to Daniel Vetter for providing a version of this patch on
      pastebin.
      
      Credits-to: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      5a65f358
    • Daniel Vetter's avatar
      drm/i915: i830M has watermarks like i855 · feb56b93
      Daniel Vetter authored
      So shuffle the checks around a bit. Also give all the structs and
      functions proper prefixes: i830_ for the dual-pipe mobile platforms
      and i845_ for the two single-pipe desktop platforms.
      
      Note that the max fifo value isn't actually correct for the i830M, but
      since we don't frob the fifo split we don't actually need it. This is
      different for some gen3 devices where we need the full fifo for self
      refresh mode.
      
      Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      feb56b93
    • Daniel Vetter's avatar
      drm/i915: Drop I915_ prefix from HAS_FBC · 3a77c4c4
      Daniel Vetter authored
      My OCD just couldn't let this slide. Spotted while reviewing Ville's
      patch to only flip planes when we have FBC.
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      3a77c4c4
    • Ville Syrjälä's avatar
      drm/i915: Don't swap planes on 830M · 38af6096
      Ville Syrjälä authored
      Looks like 830M doesn't quite like it when you try to move a plane from
      one pipe to another. It seems that the plane's old pipe has to be active
      even if the plane is already disabled, otherwise the relevant register
      just won't accept new values.
      
      The following commit:
      
       commit 1f1c2e24
       Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
       Date:   Thu Nov 28 17:30:01 2013 +0200
      
          drm/i915: Swap primary planes on gen2 for FBC
      
      caused a regression on 830M. It will attempt to swap the planes when the
      driver is loaded, but at that time only pipe A might be active, so plane
      A gets disabled, but plane B won't get enabled since pipe B is not
      active when we try to move the plane over to pipe A.
      
      There's no reason to swap planes on 830M since it doesn't support
      FBC. Change the logic a bit to limit the plane swapping to platforms
      which actually support FBC. This should avoid getting a black screen on
      830M.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      38af6096
  2. 08 Jan, 2014 5 commits
  3. 07 Jan, 2014 9 commits
    • Ville Syrjälä's avatar
      drm/i915: Simplify watermark/init_clock_gating setup · bd602544
      Ville Syrjälä authored
      Avoid duplicating the same piece of code several times by separating
      the watemark vfunc setup from the init_clock_gating vfunc setup on PCH
      platforms.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      bd602544
    • Ville Syrjälä's avatar
      drm/i915: Enable watermarks for BDW · 03dce881
      Ville Syrjälä authored
      We forgot to intialize the watermark vfuncs for BDW, and hence the
      watermarks were never updated.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      03dce881
    • Ville Syrjälä's avatar
      drm/i915: Fix watermark code for BDW · a42a5719
      Ville Syrjälä authored
      Looks like I forgot to update the ILK/SNB/IVB watermark patches to deal
      with BDW. Add the relevant BDW checks to make sure we take the HSW
      codepaths on BDW as well.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      a42a5719
    • Paulo Zanoni's avatar
      drm/i915: avoid unclaimed registers when capturing the error state · 38cc1daf
      Paulo Zanoni authored
      We're iterating over the CPU transcoders, so check for the correct
      power domain.
      
      This fixes many "unclaimed register" error messages.
      
      This can be reproduced by the IGT test mentioned below, but we still
      get a FAIL when we run it.
      
      Testcase: igt/kms_lip/flip-vs-panning-vs-hang
      Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      38cc1daf
    • Chris Wilson's avatar
      drm/i915: Flush outstanding requests before allocating new seqno · 304d695c
      Chris Wilson authored
      In very rare cases (such as a memory failure stress test) it is possible
      to fill the entire ring without emitting a request. Under this
      circumstance, the outstanding request is flushed and waited upon. After
      space on the ring is cleared, we return to emitting the new command -
      except that we just cleared the seqno allocated for this operation and
      trigger the sanity check that a request is only ever emitted with a
      valid seqno. The fix is to rearrange the code to make sure the
      allocation of the seqno for this operation is after any required flushes
      of outstanding operations.
      
      The bug exists since the preallocation was introduced in
      commit 9d773091
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Tue Nov 27 16:22:52 2012 +0000
      
          drm/i915: Preallocate next seqno before touching the ring
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      304d695c
    • Jani Nikula's avatar
      drm/i915: remove duplicate MODULE_LICENSE definition · b38538cc
      Jani Nikula authored
      Multiple definitions show up multiple times in modinfo output.
      
      There's already an identical one in i915_drv.c along with other MODULE_*
      definitions, so drop the lone one in intel_fbdev.c.
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b38538cc
    • Chris Wilson's avatar
      drm/i915: Avoid dereference past end of page array in gen8_ppgtt_insert_entries() · 6f1cc993
      Chris Wilson authored
      The bug from gen6_ppgtt_insert_entries() was replicated into
      gen8_ppgtt_insert_entries(). This applies the fix for the OOPS from the
      previous patch to the gen8 routine.
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Ben Widawsky <benjamin.widawsky@intel.com>
      Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      6f1cc993
    • Chris Wilson's avatar
      drm/i915: Avoid dereference past end of page array in gen6_ppgtt_insert_entries() · cc79714f
      Chris Wilson authored
      [   89.237347] BUG: unable to handle kernel paging request at ffff880096326000
      [   89.237369] IP: [<ffffffff81347227>] gen6_ppgtt_insert_entries+0x117/0x170
      [   89.237382] PGD 2272067 PUD 25df0e067 PMD 25de5c067 PTE 8000000096326060
      [   89.237394] Oops: 0000 [#1] SMP DEBUG_PAGEALLOC
      [   89.237404] CPU: 1 PID: 1981 Comm: gem_concurrent_ Not tainted 3.13.0-rc4+ #639
      [   89.237411] Hardware name: Intel Corporation 2012 Client Platform/Emerald Lake 2, BIOS ACRVMBY1.86C.0078.P00.1201161002 01/16/2012
      [   89.237420] task: ffff88024c038030 ti: ffff88024b130000 task.ti: ffff88024b130000
      [   89.237425] RIP: 0010:[<ffffffff81347227>]  [<ffffffff81347227>] gen6_ppgtt_insert_entries+0x117/0x170
      [   89.237435] RSP: 0018:ffff88024b131ae0  EFLAGS: 00010286
      [   89.237440] RAX: ffff880096325000 RBX: 0000000000000400 RCX: 0000000000001000
      [   89.237445] RDX: 0000000000000200 RSI: 0000000000000001 RDI: 0000000000000010
      [   89.237451] RBP: ffff88024b131b30 R08: ffff88024cc3aef0 R09: 0000000000000000
      [   89.237456] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88024cc3ae00
      [   89.237462] R13: ffff88024a578000 R14: 0000000000000001 R15: ffff88024a578ffc
      [   89.237469] FS:  00007ff5475d8900(0000) GS:ffff88025d020000(0000) knlGS:0000000000000000
      [   89.237475] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [   89.237480] CR2: ffff880096326000 CR3: 000000024d531000 CR4: 00000000001407e0
      [   89.237485] Stack:
      [   89.237488]  ffff880000000000 0000020000000000 ffff88024b23f2c0 0000000100000000
      [   89.237499]  0000000000000001 000000000007ffff ffff8801e7bf5ac0 ffff8801e7bf5ac0
      [   89.237510]  ffff88024cc3ae00 ffff880248a2ee40 ffff88024b131b58 ffffffff813455ed
      [   89.237521] Call Trace:
      [   89.237528]  [<ffffffff813455ed>] ppgtt_bind_vma+0x3d/0x60
      [   89.237534]  [<ffffffff8133d8dc>] i915_gem_object_pin+0x55c/0x6a0
      [   89.237541]  [<ffffffff8134275b>] i915_gem_execbuffer_reserve_vma.isra.14+0x5b/0x110
      [   89.237548]  [<ffffffff81342a88>] i915_gem_execbuffer_reserve+0x278/0x2c0
      [   89.237555]  [<ffffffff81343d29>] i915_gem_do_execbuffer.isra.22+0x699/0x1250
      [   89.237562]  [<ffffffff81344d91>] ? i915_gem_execbuffer2+0x51/0x290
      [   89.237569]  [<ffffffff81344de6>] i915_gem_execbuffer2+0xa6/0x290
      [   89.237575]  [<ffffffff813014f2>] drm_ioctl+0x4d2/0x610
      [   89.237582]  [<ffffffff81080bf1>] ? cpuacct_account_field+0xa1/0xc0
      [   89.237588]  [<ffffffff81080b55>] ? cpuacct_account_field+0x5/0xc0
      [   89.237597]  [<ffffffff811371c0>] do_vfs_ioctl+0x300/0x520
      [   89.237603]  [<ffffffff810757a1>] ? vtime_account_user+0x91/0xa0
      [   89.237610]  [<ffffffff810e40eb>] ?  context_tracking_user_exit+0x9b/0xe0
      [   89.237617]  [<ffffffff81083d7d>] ? trace_hardirqs_on+0xd/0x10
      [   89.237623]  [<ffffffff81137425>] SyS_ioctl+0x45/0x80
      [   89.237630]  [<ffffffff815afffa>] tracesys+0xd4/0xd9
      [   89.237634] Code: 5b 41 5c 41 5d 41 5e 41 5f 5d c3 66 0f 1f 84 00 00 00 00 00 83 45 bc 01 49 8b 84 24 78 01 00 00 65 ff 0c 25 e0 b8 00 00 8b 55 bc <4c> 8b 2c d0 65 ff 04 25 e0 b8 00 00 49 8b 45 00 48 c1 e8 2d 48
      [   89.237741] RIP  [<ffffffff81347227>] gen6_ppgtt_insert_entries+0x117/0x170
      [   89.237749]  RSP <ffff88024b131ae0>
      [   89.237753] CR2: ffff880096326000
      [   89.237758] ---[ end trace 27416ba8b18d496c ]---
      
      This bug dates back to the original introduction of the
      gen6_ppgtt_insert_entries()
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Ben Widawsky <benjamin.widawsky@intel.com>
      Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
      [danvet: Dropped cc: stable since without full ppgtt there's no way
      we'll access the last page directory with this function since that
      range is occupied (only in the allocator) with the ppgtt pdes. Without
      aliasing we can start to use that range and blow up.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      cc79714f
    • Chris Wilson's avatar
      drm/i915: Mention when we enable the Ironlake iommu workarounds · c0a7f818
      Chris Wilson authored
      The iommu and gfx on Ironlake do not like each other and require a
      big hammer to prevent hard machine hangs. In
      
      commit 5c042287
      Author: Ben Widawsky <ben@bwidawsk.net>
      Date:   Mon Oct 17 15:51:55 2011 -0700
      
          drm/i915: ILK + VT-d workaround
      
      we added the workaround, but never emitted any debug message that it was
      active. Doing so should help identify known performance regressions.
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      c0a7f818
  4. 06 Jan, 2014 1 commit
  5. 18 Dec, 2013 1 commit
  6. 17 Dec, 2013 20 commits