- 28 May, 2014 18 commits
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Paul Burton authored
If the user or bootloader sets the CCA to a value which is not suited for multi-core SMP (ie. anything non-coherent) then limit the system to using only a single core and warn the user. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch adds support for offlining CPUs via hotplug when using the CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2 things will happen: - If the CPU is part of a core which implements the MT ASE and there is at least one other VPE online within that core then the VPE will be halted by settings its TCHalt bit. - Otherwise if supported the core will be powered down via the CPC. - Otherwise the CPU will hang by executing an infinite loop. Bringing CPUs back online is then a process of either clearing the appropriate VPEs TCHalt bit or powering up the appropriate core via the CPC. Throughout the process the struct core_boot_config vpe_mask field must be maintained such that mips_cps_boot_vpes will start & stop the correct VPEs. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch adds code to generate entry & exit code for various low power states available on systems based around the MIPS Coherent Processing System architecture (ie. those with a Coherence Manager, Global Interrupt Controller & for >=CM2 a Cluster Power Controller). States supported are: - Non-coherent wait. This state first leaves the coherent domain and then executes a regular MIPS wait instruction. Power savings are found from the elimination of coherency interventions between the core and any other coherent requestors in the system. - Clock gated. This state leaves the coherent domain and then gates the clock input to the core. This removes all dynamic power from the core but leaves the core at the mercy of another to restart its clock. Register state is preserved, but the core can not service interrupts whilst its clock is gated. - Power gated. This deepest state removes all power input to the core. All register state is lost and the core will restart execution from its BEV when another core powers it back up. Because register state is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP implementation in order for the core to exit the state successfully. The code will detect which states are available on the current system during boot & generate the entry/exit code for those states. This will be used by cpuidle & hotplug implementations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The core which the CPC core-other region relates to is based upon the core-local core-other addressing register. As its name suggests this register is shared between all VPEs within a core, and if there is a possibility that multiple VPEs within a core will attempt to access another core simultaneously then locking is required. This wasn't previously a problem with the only user being cpu0 during boot, but will be an issue once hotplug is implemented & may race with other users such as cpuidle. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The start of mips_cps_core_entry is patched in order to provide the code with the address of the CM register region at a point where it will be running non-coherent with the rest of the system. However the cache wasn't being flushed after that patching which could in principle lead to secondary cores using an invalid CM base address. The patching is moved to cps_prepare_cpus since local_flush_icache_range has not been initialised at the point cps_smp_setup is called. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The core power down state for cpuidle will require that the CPS SMP implementation is in use. This patch provides a mips_cps_smp_in_use function which determines whether or not the CPS SMP implementation is currently in use. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
When hotplug and/or a powered down idle state are supported cases will arise where a non-zero VPE must be brought online without VPE 0, and it where multiple VPEs must be onlined simultaneously. This patch prepares for that by: - Splitting struct boot_config into core & VPE boot config structures, allocated one per core or VPE respectively. This allows for multiple VPEs to be onlined simultaneously without clobbering each others configuration. - Indicating which VPEs should be online within a core at any given time using a bitmap. This allows multiple VPEs to be brought online simultaneously and also indicates to VPE 0 whether it should halt after starting any non-zero VPEs that should be online within the core. For example if all VPEs within a core are offlined via hotplug and the user onlines the second VPE within that core: 1) The core will be powered up. 2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to initialise the core. 3) VPE 0 will start VPE 1 because its bit is set in the cores bitmap. 4) VPE 0 will halt itself because its bit is clear in the cores bitmap. - Moving the core & VPE initialisation to assembly code which does not make any use of the stack. This is because if a non-zero VPE is to be brought online in a powered down core then when VPE 0 of that core runs it may not have a valid stack, and even if it did then it's messy to run through parts of generic kernel code on VPE 0 before starting the correct VPE. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch allows use of the MT ASE yield instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch allows use of the wait instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch allows use of the jalr instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch allows for use of the beq instruction with labels from uasm, much as bne & others already do. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The opcode for the wait instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The opcode for the sync instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The opcode for the MT ASE yield instruction within the spec3 group was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The func field for the wait instruction was missing from inst.h - this patch adds it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
Define a macro to write to the current TCs TCHalt register. This will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This is identical to kmap_coherent apart from the cache coherency attribute used for the TLB entry, so kmap_coherent is abstracted to kmap_prot which is then called for both kmap_coherent & kmap_noncoherent. This will be used by a subsequent patch. Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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- 02 May, 2014 13 commits
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Paul Burton authored
This patch provides functions to lock & unlock access to the "core-other" register region of the CPC. Without performing appropriate locking it is possible for code using this region to be preempted or to race with code on another VPE within the same core, with one changing the core which the "core-other" region is acting upon at an inopportune time for the other. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch introduces addr_ functions in addition to the existing read_ & write_ functions. The new functions simply return the address of the appropriate CPC register rather than performing a memory access. This will be used in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
Add a mask of CPUs which are currently known to be operating coherently. This is setup initially to be all present CPUs, but in a subsequent patch CPUs in a MIPS Coherent Processing System will be cleared in this mask as they enter non-coherent idle states. This will be used in order to determine when a CPU within a CPS system may need to be powered back up, but may also be used in future to optimise away wakeups for cache operations or TLB invalidations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch adds support for generic clockevents broadcast using the a dummy clockevent device and the tick_broadcast function introduced by commit 12ad1000 "clockevents: Add generic timer broadcast function". Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
Having the GIC clockevent driver compiled should not prevent the R4K timer clockevent driver from functioning. One will be selected as the CPU local timer based upon their priorities and the other may simply be unused or in the case of the GIC timer may be used as the tick broadcast device. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
The CLOCK_EVT_FEAT_PERCPU flag indicates that a clockevent device is only configurable by the CPU for which it is registered, and thus cannot be used as the tick broadcast device. That property is true of the R4K timer, which is inaccessible from other cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
When a core enters a clock off or power down state its CP0 counter will be stopped along with it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch allows the GIC clockevent device for a CPU to be configured by another CPU. This makes GIC clockevent devices suitable for use as the tick broadcast device, where formerly the GIC timer local to the configuring CPU would have been configured incorrectly. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
Although the GIC counter will continue when a core is in a low power state and it will still trigger interrupts, the core will be incapable of servicing those interrupts rendering them useless. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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James Hogan authored
Implement assembler helper macros in asm/pm.h for platform code to use for saving context across low power states - for example suspend to RAM or powered down cpuidle states. Macros are provided for saving and restoring the main CPU context used by C code and doing important configuration which must be done very early during resume. Notably EVA needs segmentation control registers to be restored before the stack or dynamically allocated memory is accessed, so that state is saved in global data. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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James Hogan authored
Add a CPU power management callback for the r4k TLB which reconfigures it after the CPU leaves a powered down state. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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James Hogan authored
Implement a CPU power management callback for the r4k cache, to set up coherency again after leaving a powered down state. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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James Hogan authored
Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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- 24 Apr, 2014 1 commit
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James Hogan authored
Add a CPU power management notifier callback for preserving general CPU context. The CPU PM callbacks will be triggered by the powering down of CPU cores, for example by cpuidle drivers & in the future by suspend to RAM implementations. The current state preserved is mostly related to the process context: - FPU - DSP - ASID - UserLocal - Watch registers Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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- 20 Apr, 2014 5 commits
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Linus Torvalds authored
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git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds authored
Pull slave-dmaengine fixes from Vinod Koul: "Back from long weekend here in India and now the time to send fixes for slave dmaengine. - Dan's fix of sirf xlate code - Jean's fix for timberland - edma fixes by Sekhar for SG handling and Yuan for changing init call" * 'fixes' of git://git.infradead.org/users/vkoul/slave-dma: dma: fix eDMA driver as a subsys_initcall dmaengine: sirf: off by one in of_dma_sirfsoc_xlate() platform: Fix timberdale dependencies dma: edma: fix incorrect SG list handling
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git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommuLinus Torvalds authored
Pull iommu fixes from Joerg Roedel: "Fixes for regressions: - fix wrong IOMMU enumeration causing some SCSI device drivers initialization failures - ARM-SMMU fixes for a panic condition and a wrong return value" * tag 'iommu-fixes-v3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/arm-smmu: fix panic in arm_smmu_alloc_init_pte iommu/arm-smmu: Return 0 on unmap failure iommu/vt-d: fix bug in matching PCI devices with DRHD/RMRR descriptors iommu/vt-d: Fix get_domain_for_dev() handling of upstream PCIe bridges iommu/vt-d: fix memory leakage caused by commit ea8ea460
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull perf tooling fixes from Ingo Molnar: "Three small tooling fixes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf tools: Improve error reporting perf tools: Adjust symbols in VDSO perf kvm: Fix 'Min time' counting in report command
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Ingo Molnar authored
Merge tag 'perf-urgent-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf into perf/urgent Pull perf/urgent fixes from Jiri Olsa: User visible changes: * Adjust symbols in VDSO to properly resolve its function names (Vladimir Nikulichev) * Improve error reporting for record session failure (Adrien BAK) * Fix 'Min time' counting in report command (Alexander Yarygin) Signed-off-by: Jiri Olsa <jolsa@redhat.com> Signed-off-by: Ingo Molnar <mingo@kernel.org>
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- 19 Apr, 2014 3 commits
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Adrien BAK authored
In the current version, when using perf record, if something goes wrong in tools/perf/builtin-record.c:375 session = perf_session__new(file, false, NULL); The error message: "Not enough memory for reading per file header" is issued. This error message seems to be outdated and is not very helpful. This patch proposes to replace this error message by "Perf session creation failed" I believe this issue has been brought to lkml: https://lkml.org/lkml/2014/2/24/458 although this patch only tackles a (small) part of the issue. Additionnaly, this patch improves error reporting in tools/perf/util/data.c open_file_write. Currently, if the call to open fails, the user is unaware of it. This patch logs the error, before returning the error code to the caller. Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Adrien BAK <adrien.bak@metascale.org> Link: http://lkml.kernel.org/r/1397786443.3093.4.camel@beast [ Reorganize the changelog into paragraphs ] [ Added empty line after fd declaration in open_file_write ] Signed-off-by: Jiri Olsa <jolsa@redhat.com>
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Vladimir Nikulichev authored
pert-report doesn't resolve function names in VDSO: $ perf report --stdio -g flat,0.0,15,callee --sort pid ... 8.76% 0x7fff6b1fe861 __gettimeofday ACE_OS::gettimeofday() ... In this case symbol values should be adjusted the same way as for executables, relocatable objects and prelinked libraries. After fix: $ perf report --stdio -g flat,0.0,15,callee --sort pid ... 8.76% __vdso_gettimeofday __gettimeofday ACE_OS::gettimeofday() Signed-off-by: Vladimir Nikulichev <nvs@tbricks.com> Tested-by: Namhyung Kim <namhyung@kernel.org> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: http://lkml.kernel.org/r/969812.163009436-sendEmail@nvsSigned-off-by: Jiri Olsa <jolsa@redhat.com>
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Alexander Yarygin authored
Every event in the perf-kvm has a 'stats' structure, which contains max/min/average/etc times of handling this event. The problem is that the 'perf-kvm stat report' command always shows that 'min time' is 0us for every event. Example: # perf kvm stat report Analyze events for all VCPUs: VM-EXIT Samples Samples% Time% Min Time Max Time Avg time [..] 0xB2 MSCH 12 0.07% 0.00% 0us 8us 7.31us ( +- 2.11% ) 0xB2 CHSC 12 0.07% 0.00% 0us 18us 9.39us ( +- 9.49% ) 0xB2 STPX 8 0.05% 0.00% 0us 2us 1.88us ( +- 7.18% ) 0xB2 STSI 7 0.04% 0.00% 0us 44us 16.49us ( +- 38.20% ) [..] This happens because the 'stats' structure is not initialized and stats->min equals to 0. Lets initialize the structure for every event after its allocation using init_stats() function. This initializes stats->min to -1 and makes 'Min time' statistics counting work: # perf kvm stat report Analyze events for all VCPUs: VM-EXIT Samples Samples% Time% Min Time Max Time Avg time [..] 0xB2 MSCH 12 0.07% 0.00% 6us 8us 7.31us ( +- 2.11% ) 0xB2 CHSC 12 0.07% 0.00% 7us 18us 9.39us ( +- 9.49% ) 0xB2 STPX 8 0.05% 0.00% 1us 2us 1.88us ( +- 7.18% ) 0xB2 STSI 7 0.04% 0.00% 1us 44us 16.49us ( +- 38.20% ) [..] Signed-off-by: Alexander Yarygin <yarygin@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Ahern <dsahern@gmail.com> Link: http://lkml.kernel.org/r/1397053319-2130-3-git-send-email-borntraeger@de.ibm.com [ Fixing the perf examples changelog output ] Signed-off-by: Jiri Olsa <jolsa@redhat.com>
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