- 14 Jul, 2017 40 commits
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Jim Qu authored
Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Dan Carpenter authored
This is just future proofing code, not something that can be triggered in real life. We're testing to make sure we don't shift wrap when we do "1ull << i" so "i" has to be in the 0-63 range. If it's 64 then we have gone too far. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Alex Deucher authored
This allows us to read the vbios image directly from ROM. This is already implemented for other asics, but was not yet available for SI. Acked-by:
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Alex Deucher authored
Maybe a leftover from bringup? Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Alex Deucher authored
Rather than the legacy atombios version. Acked-by:
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Alex Deucher authored
The information has moved to different tables, notably smu_info for core refclk and umc_info for mem refclk. Acked-by:
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Jay Cornwall authored
A subset of VM fault types currently send retry XNACK to the client. This causes a storm of interrupts from the VM to the host. Until the storm is throttled by other means send no-retry XNACK for all fault types instead. No change in behavior to the client which will stall indefinitely with the current configuration in any case. Improves system stability under GC or MMHUB faults. Signed-off-by:
Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
John Bridgman <John.Bridgman@amd.com> Acked-by:
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Yong Zhao authored
Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
Oded Gabbay <oded.gabbay@gmail.com> Reviewed-by:
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Felix Kuehling authored
Set a configurable SDMA phase quantum when enabling SDMA context switching. The default value significantly reduces SDMA latency in page table updates when user-mode SDMA queues have concurrent activity, compared to the initial HW setting. Signed-off-by:
Andres Rodriguez <andres.rodriguez@amd.com> Reviewed-by:
Shaoyun Liu <shaoyun.liu@amd.com> Acked-by:
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Felix Kuehling authored
Enable SDMA context switching on CIK (copied from sdma_v3_0.c). Signed-off-by:
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shaoyunl authored
For GFX context, the ATC bit in SDMA*_GFX_VIRTUAL_ADDRESS can be cleared to perform in VM mode. For RLC context, to support ATC mode , ATC bit in SDMA*_RLC*_VIRTUAL_ADDRESS should be set. SDMA_CNTL.ATC_L1_ENABLE bit is global setting that enables the L1-L2 translation for ATC address. Signed-off-by:
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Michel Dänzer authored
This gives BOs which haven't been accessed by the CPU since they were moved to visible VRAM another chance to stay in VRAM when another BO needs to go to visible VRAM. This should allow BOs to stay in VRAM longer in some cases. v2: * Only do this for BOs which don't have the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag set. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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John Brooks authored
There is no need for page faults to force BOs into visible VRAM if it's full, and the time it takes to do so is great enough to cause noticeable stuttering. Add GTT as a possible placement so that if visible VRAM is full, page faults move BOs to GTT instead of evicting other BOs from VRAM. Suggested-by:
John Brooks <john@fastquake.com> Reviewed-by:
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John Brooks authored
When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED. This allows it to potentially later move to invisible VRAM if the CPU does not access it again. Setting the CPU_ACCESS flag in amdgpu_bo_fault_reserve_notify() also means that we can remove the loop to restrict lpfn to the end of visible VRAM, because amdgpu_ttm_placement_init() will do it for us. v3 [Michel Dänzer] * Use AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED instead of a new flag (Christian König) * Clear flag in amdgpu_bo_move instead of amdgpu_move_ram_vram (Christian) * Explicitly mention amdgpu_bo_fault_reserve_notify in amdgpu_bo_move * Also clear flag in amdgpu_bo_create_restricted Suggested-by:
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John Brooks authored
The BO move throttling code is designed to allow VRAM to fill quickly if it is relatively empty. However, this does not take into account situations where the visible VRAM is smaller than total VRAM, and total VRAM may not be close to full but the visible VRAM segment is under pressure. In such situations, visible VRAM would experience unrestricted swapping and performance would drop. Add a separate counter specifically for moves involving visible VRAM, and check it before moving BOs there. v2: Only perform calculations for separate counter if visible VRAM is smaller than total VRAM. (Michel Dänzer) v3: [Michel Dänzer] * Use BO's location rather than the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag to determine whether to account a move for visible VRAM in most cases. * Use a single if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { block in amdgpu_cs_get_threshold_for_moves. Fixes: 95844d20 (drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit (v2)) Signed-off-by: -
John Brooks authored
Allow specifying a limit on visible VRAM via a module parameter. This is helpful for testing performance under visible VRAM pressure. v2: Add cast to 64-bit (Christian König) Signed-off-by:
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Christian König authored
Limit the default GART size and save a lot of VRAM. Signed-off-by:
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Christian König authored
This allows setting the gtt size independent of the gart size. v2: fix copy and paste typo Signed-off-by:
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Christian König authored
We should only cover the GART size with the GTT manager. Signed-off-by:
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Christian König authored
Rename symbols from gtt_ to gart_ as appropriate. Signed-off-by:
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Christian König authored
Not used any more. Signed-off-by:
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Christian König authored
No functional change, just cleanup. v2: rebased, keep gart name. Signed-off-by:
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Alex Deucher authored
Rather than checking the CONGIG_MEMSIZE register as that may not be reliable on some APUs. v2: The scratch register is only used on CIK+ Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Alex Deucher authored
Call nbio init registers on hw_init to set up any nbio registers that need initialization at hw init time. Acked-by:
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Alex Deucher authored
Used for nbio registers that need to be initialized. Currently only used for a golden setting that got missed on some boards. Acked-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
- v2: rename param 'en' as 'lock' Signed-off-by:
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Evan Quan authored
Signed-off-by:
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Evan Quan authored
Signed-off-by:
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Evan Quan authored
- v2: added missing spinlock init Signed-off-by:
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Evan Quan authored
Signed-off-by:
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Christian König authored
Use the TTM values instead of the hardware config here. Signed-off-by:
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Christian König authored
We can finally remove this now. v2: remove now unused max_size variable as well. Signed-off-by:
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Christian König authored
No need to map BOs to GTT on eviction and intermediate transfers any more. Signed-off-by:
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Christian König authored
This way we don't need to map the full BO at a time any more. v2: use fixed windows for src/dst Signed-off-by:
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Christian König authored
This allows us to write the mapped PTEs into an IB instead of the table directly. v2: fix build with debugfs enabled, remove unused assignment Signed-off-by:
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Christian König authored
We want to use them as remap address space. Signed-off-by:
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Colin Ian King authored
The arrays pctl0_data and pctl1_data do not need to be in global scope, so them both static. Cleans up sparse warnings: symbol 'pctl0_data' was not declared. Should it be static? symbol 'pctl1_data' was not declared. Should it be static? Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
Get it from the system info table. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Alex Deucher authored
Implement support using the new atomfirmware system info table. Reviewed-by:
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