- 27 Jun, 2013 40 commits
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Alex Deucher authored
Needed to properly handle dynamic state adjustment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Needed to properly handle dynamic state adjustment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Needed to properly handle dynamic state adjustment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for cayman asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: fold in tdp fix v3: fix indentation v4: fix 64 bit div v5: attempt to fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
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Alex Deucher authored
Use a dedicated copy of the current power state since we may have to adjust it on the fly. v2: fix up redundant state sets Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Use a dedicated copy of the current power state since we may have to adjust it on the fly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Use a dedicated copy of the current power state since we may have to adjust it on the fly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Driver needs this information to validate power states. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This data will be needed for dpm on newer asics. v2: fix typo in rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When using UVD, the driver must switch to a special UVD power state. In the CS ioctl, switch to the power state and schedule work to change the power state back, when the work comes up, check if uvd is still busy and if not, switch back to the user state, otherwise, reschedule the work. Note: We really need some better way to decide when to switch out of the uvd power state. Switching power states while playback is active make uvd angry. V2: fix locking. V3: switch from timer to delayed work V4: check fence driver for UVD jobs, reduce timeout to 1 second and rearm timeout on activity v5: rebase on new dpm tree v6: rebase on interim uvd on demand changes v7: fix UVD when DPM is disabled v8: unify non-DPM and DPM UVD handling v9: remove leftover idle work struct Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
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Alex Deucher authored
v2: fix typo noticed by Dan Carpenter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for trinity asics. This includes: - clockgating - powergating - dynamic engine clock scaling - dynamic voltage scaling set radeon.dpm=1 to enable it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for sumo asics. This includes: - clockgating - powergating - dynamic engine clock scaling - dynamic voltage scaling set radeon.dpm=1 to enable it. v2: fix indention Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
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Alex Deucher authored
This adds dpm support for btc asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage v3: attempt to fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for evergreen asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage, rename ulv struct v3: fix thermal interrupt check notices by Jerome v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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Alex Deucher authored
This adds dpm support for rs780/rs880 asics. This includes: - clockgating - dynamic engine clock scaling - dynamic voltage scaling set radeon.dpm=1 to enable it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are shared by rs780/rs880, rv6xx, and newer chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds the common dpm (dynamic power management) infrastructure: - dpm callbacks - dpm init/fini/suspend/resume - dpm power state selection No device specific code is enabled yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Has a different dpm controller than r600. v2: rebase on gpu reset changes v3: rebase on get_xclk changes v4: update rptr/wtpr callbacks Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
dpm needs access to atombios data and command tables for setup and calculation of a number of parameters. v2: endian fix v3: fix mc reg table bug Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Avoids confusion and duplication. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
v2: fix up for latest reset changes v3: use CP for pt updates for now v4: update for 2 level PTs v5: update for ib_parse removal v6: vm_flush api change v7: rebase v8: fix gfx ring function pointers v9: fix vm_set_page function params v10: update for compute changes v11: cleanup for release v12: update rptr/wptr callbacks Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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