- 01 Feb, 2019 17 commits
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Jayant Shekhar authored
Remove unused functions and macros from files handling dpu hardware interrupts. changes in v2: Removed clear_interrupt_status (Jordan Crouse) changes in v3: Changed commit text Signed-off-by:
Jayant Shekhar <jshekhar@codeaurora.org> Signed-off-by:
Sean Paul <seanpaul@chromium.org>
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Jayant Shekhar authored
Remove unused functions from dpu plane interface and unused variables from dpu plane state structure. Reviewed-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
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Jayant Shekhar authored
Remove enum dpu_iommu_domain from dpu mdss as its unused. Remove unnecessary comment for variable which is already removed. Signed-off-by:
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Jeykumar Sankaran authored
Bail out KMS hw init on display initialization failures with proper error logging. changes in v3: - introduced in the series changes in v4: - avoid duplicate return on errors (Sean Paul) - avoid spamming errors on failures (Jordon Crouse) Signed-off-by:Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:
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Jeykumar Sankaran authored
Fix intf_type description in msm_disp_info to show that it represents drm encoder mode of the display. changes in v3: - introduced in the series changes in v4: - none Signed-off-by:
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Stephen Boyd authored
Devices that make up DPU, i.e. graphics card, request their interrupts from this "virtual" interrupt chip. The interrupt chip builds upon a GIC SPI interrupt that raises high when any of the interrupts in the DPU's irq status register are triggered. From the kernel's perspective this is a chained irq chip, so requesting a flow handler for the GIC SPI and then calling generic IRQ handling code from that irq handler is not completely proper. It's better to convert this to a chained irq so that the GIC SPI irq doesn't appear in /proc/interrupts, can't have CPU affinity changed, and won't be accounted for with irq stats. Doing this also silences a recursive lockdep warning because we can specify a different lock class for the chained interrupts, silencing a warning that is easy to see with 'threadirqs' on the kernel commandline. WARNING: inconsistent lock state 4.19.10 #76 Tainted: G W -------------------------------- inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. irq/40-dpu_mdss/203 [HC0[0]:SC0[2]:HE1:SE0] takes: 0000000053ea9021 (&irq_desc_lock_class){?.-.}, at: handle_level_irq+0x34/0x26c {IN-HARDIRQ-W} state was registered at: lock_acquire+0x244/0x360 _raw_spin_lock+0x64/0xa0 handle_fasteoi_irq+0x54/0x2ec generic_handle_irq+0x44/0x5c __handle_domain_irq+0x9c/0x11c gic_handle_irq+0x208/0x260 el1_irq+0xb4/0x130 arch_cpu_idle+0x178/0x3cc default_idle_call+0x3c/0x54 do_idle+0x1a8/0x3dc cpu_startup_entry+0x24/0x28 rest_init+0x240/0x270 start_kernel+0x5a8/0x6bc irq event stamp: 18 hardirqs last enabled at (17): [<ffffff9042385e80>] _raw_spin_unlock_irq+0x40/0xc0 hardirqs last disabled at (16): [<ffffff904237a1f4>] __schedule+0x20c/0x1bbc softirqs last enabled at (0): [<ffffff9040f318d0>] copy_process+0xb50/0x3964 softirqs last disabled at (18): [<ffffff9041036364>] local_bh_disable+0x8/0x20 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); <Interrupt> lock(&irq_desc_lock_class); *** DEADLOCK *** no locks held by irq/40-dpu_mdss/203. stack backtrace: CPU: 0 PID: 203 Comm: irq/40-dpu_mdss Tainted: G W 4.19.10 #76 Call trace: dump_backtrace+0x0/0x2f8 show_stack+0x20/0x2c __dump_stack+0x20/0x28 dump_stack+0xcc/0x10c mark_lock+0xbe0/0xe24 __lock_acquire+0x4cc/0x2708 lock_acquire+0x244/0x360 _raw_spin_lock+0x64/0xa0 handle_level_irq+0x34/0x26c generic_handle_irq+0x44/0x5c dpu_mdss_irq+0x64/0xec irq_forced_thread_fn+0x58/0x9c irq_thread+0x120/0x1dc kthread+0x248/0x260 ret_from_fork+0x10/0x18 ------------[ cut here ]------------ irq 169 handler irq_default_primary_handler+0x0/0x18 enabled interrupts Cc: Sean Paul <seanpaul@chromium.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Jayant Shekhar <jshekhar@codeaurora.org> Cc: Rajesh Yadav <ryadav@codeaurora.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Jeykumar Sankaran authored
hw_mdp block is common for displays. No need to reserve per display. changes in v2: - use IS_ERR for error checking (Jordan Crouse) Signed-off-by:
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Jeykumar Sankaran authored
struct dpu_hw_blk has hw block type info. Remove duplicate type tracking in struct dpu_rm_hw_blk. changes in v2: - remove redundant type in trace api's (Sean Paul) Signed-off-by:
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Jeykumar Sankaran authored
Not actively used. Clean up the crtc mixer struct. changes in v2: - none Signed-off-by:
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Jeykumar Sankaran authored
Definition was removed already. Clean up header declaration. changes in v2: - none Signed-off-by:
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Jeykumar Sankaran authored
Not used. Remove from RM. changes in v2: - none Signed-off-by:
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Jeykumar Sankaran authored
RM was equipped with reservation tracking structure RSVP to cache HW reservation of displays for certain clients where atomic_checks (atomic commit with TEST_ONLY) for all the displays are called before their respective atomic_commits. Since DPU doesn't support the sequence anymore, clean up the support from RM. Replace rsvp with the corresponding encoder id to tag the HW blocks reserved. It prepares DPU to get rid of RM altogether and track reservations using private states. changes in v2: - none Signed-off-by:
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Fritz Koenig authored
allow_fb_modifiers needs to be set before drm_universal_plane_init is called. Signed-off-by:
Fritz Koenig <frkoenig@google.com> Signed-off-by:
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Fritz Koenig authored
Pass list of supported modifiers to plane init. Signed-off-by:
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Fritz Koenig authored
Filter planes based on the supported modifiers Signed-off-by:
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Fritz Koenig authored
Simplify the initilization of a list of formats by passing the list in directly instead of copying it from one structure to another. Signed-off-by:
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Fritz Koenig authored
Signed-off-by:
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- 29 Jan, 2019 10 commits
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Jordan Crouse authored
Commit 24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings") mistakenly omitted the GMU bindings as seen in [1]. Return them to their rightful place. [1] https://patchwork.freedesktop.org/patch/268679/Signed-off-by:Rob Herring <robh@kernel.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Jordan Crouse authored
Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets. Signed-off-by:
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Arnd Bergmann authored
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:368:13: error: 'dpu_plane_danger_signal_ctrl' defined but not used [-Werror=unused-function] Fixes: 7b2e7ade ("drm/msm/dpu: Make dpu_plane_danger_signal_ctrl void") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Anders Roxell <anders.roxell@linaro.org> Signed-off-by:
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Joe Perches authored
Add a few __printf attribute specifiers to routines that could use them. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Douglas Anderson authored
The bindings for Qualcomm opp levels changed after being Acked but before landing. Thus the code in the GPU driver that was relying on the old bindings is now broken. Let's change the code to match the new bindings by adjusting the old string 'qcom,level' to the new string 'opp-level'. See the patch ("dt-bindings: opp: Introduce opp-level bindings"). NOTE: we will do additional cleanup to totally remove the string from the code and use the new dev_pm_opp_get_level() but we'll do it in a future patch. This will facilitate getting the important code fix in sooner without having to deal with cross-maintainer dependencies. This patch needs to land before the patch ("arm64: dts: sdm845: Add gpu and gmu device nodes") since if a tree contains the device tree patch but not this one you'll get a crash at bootup. Fixes: 4b565ca5 ("drm/msm: Add A6XX device support") Signed-off-by:Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Rob Clark authored
Signed-off-by: -
Jordan Crouse authored
Each GPU core only uses one interrupt so we don't to look up an interrupt by name and thereby we don't need interrupt-names. Signed-off-by:
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Jordan Crouse authored
Every GPU core only has one interrupt so there isn't any value in looking up the interrupt by name. Remove the name (which is legacy anyway) and use platform_get_irq() instead. Signed-off-by:
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Arnd Bergmann authored
When debugfs is disabled, but coredump is turned on, the adreno driver fails to build: drivers/gpu/drm/msm/adreno/a3xx_gpu.c:460:4: error: 'struct msm_gpu_funcs' has no member named 'show' .show = adreno_show, ^~~~ drivers/gpu/drm/msm/adreno/a3xx_gpu.c:460:11: note: (near initialization for 'funcs.base') drivers/gpu/drm/msm/adreno/a3xx_gpu.c:460:11: error: initialization of 'void (*)(struct msm_gpu *, struct msm_gem_submit *, struct msm_file_private *)' from incompatible pointer type 'void (*)(struct msm_gpu *, struct msm_gpu_state *, struct drm_printer *)' [-Werror=incompatible-pointer-types] drivers/gpu/drm/msm/adreno/a3xx_gpu.c:460:11: note: (near initialization for 'funcs.base.submit') drivers/gpu/drm/msm/adreno/a4xx_gpu.c:546:4: error: 'struct msm_gpu_funcs' has no member named 'show' drivers/gpu/drm/msm/adreno/a5xx_gpu.c:1460:4: error: 'struct msm_gpu_funcs' has no member named 'show' drivers/gpu/drm/msm/adreno/a6xx_gpu.c:769:4: error: 'struct msm_gpu_funcs' has no member named 'show' drivers/gpu/drm/msm/msm_gpu.c: In function 'msm_gpu_devcoredump_read': drivers/gpu/drm/msm/msm_gpu.c:289:12: error: 'const struct msm_gpu_funcs' has no member named 'show' Adjust the #ifdef to make it build again. Fixes: c0fec7f5 ("drm/msm/gpu: Capture the GPU state on a GPU hang") Signed-off-by: -
Kristian H. Kristensen authored
Prevents deadlock when fifo is full and reader closes file. Signed-off-by:
Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
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- 24 Jan, 2019 2 commits
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 5.1: UAPI Changes: - Addition of the Allwinner tiled format modifier Cross-subsystem Changes: Core Changes: - dma-buf documentation improvements - Removal of now unused fbdev helpers - Addition of new drm fbdev helpers - Improvements to tinydrm - Addition of new drm_fourcc helpers - Impromevents to i2c-over-aux to handle I2C_M_STOP Driver Changes: - Add support for the TI DS90C185 LVDS bridge - Improvements to the thc63lvdm83d bridge - Improvements to sun4i YUV and scaler support - Fix to the powerdown sequence of panel-innolux Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190123110317.h4tovujaydo2bfz2@flea
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
- Unwind failure on pinning the gen7 PPGTT (Chris) - Fastset updates to make sure DRRS and PSR are properly enabled (Hans) - Header include clean-up (Brajeswar, Jani) - Improvements and clean-up on debugfs (Chris, Jani) - Avoid division by zero on CNL clocks setup (Xiao) - Restrict PSMI context load w/a to Haswell GT1 (Chris) - Remove HW semaphores for gen7 inter-engine sync (Chris) - Pull the render flush into breadcrumb emission (Chris) - i915_params copy and free helpers and other reorgs and docs (Jani) - Remove has_pooled_eu static initializer (Tvrtko) - Updates on kerneldoc (Chris) - Remove redundant trailing request flush (Chris) - ringbuffer irq seqno fixes and clean-up (Chris) - splitting off runtime device info and other clean-up around (Jani) - Selftests improvements (Chris, Daniele) - Flush RING_IMR changes before changing the global GT IMR on gen6 and HSW (Chris) - Some improvements and fixes around GPU reset and GPU hang report (Chris) - Remove partial attempt to swizzle on pread/pwrite (Chris) - Return immediately if trylock fails for direct-reclaim (Chris) - Downgrade scare message for unknown HuC firmware (Jani) - ACPI / PMIC for MIPI / DSI (Hans) - Reduce i915_request_alloc retirement to local context (Chris) - Init per-engine WAs for all engines (Daniele) - drop DPF code for gen8+ (Daniele) - Guard error capture against unpinned vma (Chris) - Use mutex_lock_killable from inside the shrinker (Chris) - Removing pooling from struct_mutex from vmap shrinker (Chris) Signed-off-by:
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- 22 Jan, 2019 3 commits
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Hsin-Yi, Wang authored
Move mipi_dsi_dcs_set_display_off() from innolux_panel_disable() to innolux_panel_unprepare(), so they are consistent with innolux_panel_enable() and innolux_panel_prepare(). This also fixes some mode check and irq timeout issue in MTK dsi code. Since some dsi code (e.g. mtk_dsi) have following call trace: 1. drm_panel_disable(), which calls innolux_panel_disable() 2. switch to cmd mode 3. drm_panel_unprepare(), which calls innolux_panel_unprepare() However, mtk_dsi needs to be in cmd mode to be able to send commands (e.g. mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sleep_mode()), so we need these functions to be called after the switch to cmd mode happens, i.e. in innolux_panel_unprepare. Signed-off-by:
Hsin-Yi, Wang <hsinyi@chromium.org> Signed-off-by:
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Ville Syrjälä authored
Consult the I2C_M_STOP flag to determine whether to set the MOT bit or not. Makes it possible to send multiple messages in one go with stop+start generated between the messages (as opposed nothing or repstart depending on whether thr address/rw changed). Not sure anyone has actual use for this but figured I'd handle it since I started to look at that flag for MST remote i2c xfers. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180928180403.22499-3-ville.syrjala@linux.intel.comReviewed-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
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Jani Nikula authored
We have a wrapper for a reason. Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190121112758.10978-1-jani.nikula@intel.com
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- 21 Jan, 2019 2 commits
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Sam Ravnborg authored
Reversed logic when writing the original comment, now fixed. Fixes: e9eafcb5 ("drm: move drm_can_sleep() to drm_util.h") Reported-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190120171217.12508-1-sam@ravnborg.org
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YueHaibing authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/stm/ltdc.c: In function 'ltdc_plane_atomic_check': drivers/gpu/drm/stm/ltdc.c:694:13: warning: variable 'src_y' set but not used [-Wunused-but-set-variable] u32 src_x, src_y, src_w, src_h; ^ ^ drivers/gpu/drm/stm/ltdc.c:694:6: warning: variable 'src_x' set but not used [-Wunused-but-set-variable] u32 src_x, src_y, src_w, src_h; ^ Signed-off-by:YueHaibing <yuehaibing@huawei.com> Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/1538131180-34108-1-git-send-email-yuehaibing@huawei.com
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- 18 Jan, 2019 6 commits
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Paul Kocialkowski authored
This adds the appropriate device-tree compatible for hooking frontend support for the A20. Since the hardware is very similar to the A10, it shares the same quirks (which were already introduced). Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-24-paul.kocialkowski@bootlin.com
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Paul Kocialkowski authored
This adds the appropriate device-tree compatible and quirk data for hooking frontend support for the A20. It supports the FIR coefficients ready bit but not the access control bit. It also takes different phase values than the A33 for these coefficients. The compatible is already used in the A10 device-tree and already documented in the device-tree bindings. Signed-off-by:
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Maxime Ripard authored
The FIR filters phase depend on the SoC, so let's move it to our quirks structure instead of removing them. Reviewed-by:
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Maxime Ripard authored
The COEF_RDY bit isn't found in all the SoCs featuring some variant of the frontend. Add it to our quirks structure. Reviewed-by:
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Maxime Ripard authored
The COEF_RDY bit is used to tell the hardware that new FIR filters coefficients have been written to the registers and that the hardware should take them into account starting next frame. Reviewed-by:
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Maxime Ripard authored
The ACCESS_CTRL bit is not found on all the variants of the frontend, so let's introduce a structure that will hold whether or not we need to set it, and associate it with the compatible. This will be extended for further similar quirks later on. Reviewed-by:
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