- 11 May, 2016 32 commits
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Aneesh Kumar K.V authored
The usage in mm mmu_context_nohash.c is bogus, because we set the context.id value to MMU_NO_CONTEXT 4 lines previously in the same function, meaning slice_mm_new_context() will always be true. The book3s 64 usage was removed in the previous commit. So remove it as unused. Signed-off-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Aneesh Kumar K.V authored
As part of the radix support we switched Book3s64 to use a value of ~0 for MMU_NO_CONTEXT. That is because id 0 is special on radix. However that broke the logic in init_new_context(). The code there needs to differentiate between a newly allocated context and one inherited via fork. Previously it worked because a newly allocated context has an id of zero (because it was just memset() to zero), which used to match MMU_NO_CONTEXT, and therefore slice_mm_new_context() did the right thing. Instead check against a context.id value of zero instead of using slice_mm_new_context(). Without this patch we never call slice_set_user_psize(), and end up with a slice psize value of zero and we always end up using 4K HPTE. Fixes: 1a472c9d ("powerpc/mm/radix: Add tlbflush routines") Signed-off-by:
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Valentin Rothberg authored
It's CONFIG_PPC_STD_MMU_64 not ... CONFIG_PPC_MMU_STD_64. Fixes: 11ffc1cfa4c2 ("powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code") Signed-off-by:Valentin Rothberg <valentinrothberg@gmail.com> Reviewed-by:
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Aneesh Kumar K.V authored
Add #defines for Power ISA 3.0 software defined bits. Signed-off-by:
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Aneesh Kumar K.V authored
We use the existing "ibm,pa-features" device-tree property to enable Radix MMU mode. This means we default to hash mode unless firmware tells us it's OK to start using Radix mode. Signed-off-by:
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Aneesh Kumar K.V authored
This adds THP support for 4K Linux page size config with radix. We still don't do THP with 4K Linux page size and hash page table. Hash page table needs a 16MB hugepage and we can't do THP with 16MM hugepage and 4K Linux page size. We add missing functions to 4K hash config to get it to build and hash__has_transparent_hugepage() makes sure we don't enable THP for 4K hash config. To catch wrong usage of THP related with 4K config, we add BUG() in those dummy functions we added to get it compile. Signed-off-by:
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Aneesh Kumar K.V authored
The deposited pgtable_t is a pte fragment hence we cannot use page->lru for linking then together. We use the first two 64 bits for pte fragment as list_head type to link all deposited fragments together. On withdraw we properly zero then out. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
Only code movement in this patch. No functionality change. Signed-off-by:
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Aneesh Kumar K.V authored
We have hugepage at the pmd level with 4K radix config. Hence we don't need to use hugepd format with radix. Signed-off-by:
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Aneesh Kumar K.V authored
With 4K page size radix config our level 1 page table size is 64K and it should be naturally aligned. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
Radix doesn't use the slice framework to find the page size. Hence use vma to find the page size. Signed-off-by:
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Aneesh Kumar K.V authored
In this patch we make the number of pte fragments per level 4 page table page a variable. Radix level 4 table size is 256 bytes and hence we can have 256 fragments per level 4 page. We don't update the fragment count in this patch. We need to do performance measurements to find the right value for fragment count. Signed-off-by:
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Aneesh Kumar K.V authored
With radix there is no MMU cache. Hence we don't need to do anything in update_mmu_cache(). Signed-off-by:
Balbir Singh <bsingharora@gmail.com> Signed-off-by:
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Aneesh Kumar K.V authored
The vmalloc range differs between hash and radix config. Hence make VMALLOC_START and related constants a variable which will be runtime initialized depending on whether hash or radix mode is active. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
This patch switches 4K Linux page size config to use pte_t * type instead of struct page * for pgtable_t. This simplifies the code a lot and helps in consolidating both 64K and 4K page allocator routines. The changes should not have any impact, because we already store physical address in the upper level page table tree and that implies we already do struct page * to physical address conversion. One change to note here is we move the pgtable_page_dtor() call for nohash to pte_fragment_free_mm(). The nohash related change is due to the related changes in pgtable_64.c. Signed-off-by:
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Aneesh Kumar K.V authored
Only code cleanup. No functionality change. Signed-off-by:
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Aneesh Kumar K.V authored
Simplify the code by dropping 4-level page table #ifdef. We are always 4-level now. Signed-off-by:
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Aneesh Kumar K.V authored
This reverts pgalloc related changes WRT implementing 4-level page table for 64K Linux page size and storing of physical address in higher level page tables since they are only applicable to book3s64 variant and we now have a separate copy for book3s64. This helps to keep these headers simpler. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
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Aneesh Kumar K.V authored
This moves the nohash variant of pgalloc headers to nohash/ directory Signed-off-by:
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Aneesh Kumar K.V authored
This patch start to make a book3s variant for pgalloc headers. We have multiple book3s specific changes such as: * 4 level page table * store physical address in higher level table * use pte_t * for pgtable_t Having a book3s64 specific variant helps to keep code simpler and remove lots of #ifdef around code. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
Hash needs special get_unmapped_area() handling because of limitations around base page size, so we have to set HAVE_ARCH_UNMAPPED_AREA. With radix we don't have such restrictions, so we could use the generic code. But because we've set HAVE_ARCH_UNMAPPED_AREA (for hash), we have to re-implement the same logic as the generic code. Signed-off-by:
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Aneesh Kumar K.V authored
On return from RTAS we access the paca variables and we have 64 bit disabled. This requires us to limit paca in 32 bit range. Fix this by setting ppc64_rma_size to first_memblock_size/1G range. Signed-off-by:
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Aneesh Kumar K.V authored
Radix doesn't need slice support. Catch incorrect usage of slice code when radix is enabled. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
We also use MMU_FTR_RADIX to branch out from code path specific to hash. No functionality change. Signed-off-by:
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Aneesh Kumar K.V authored
We are going to add asm changes in the follow up patches. Add the feature bit now so that we can get it all build. mpe: When CONFIG_PPC_RADIX_MMU=n we omit MMU_FTR_RADIX from the MMU_FTRS_POSSIBLE mask. This allows the compiler to work out that those checks will always be false and so the code can be elided completely. Note we do *not* define MMU_FTR_RADIX to 0 in the RADIX_MMU=n case, because that doesn't work with the ASM_FTR patching. In particular an IF_SET section will result in a mask and value of zero, which is always true, meaning the section *won't* be patched, which is the opposite of what we want. Signed-off-by:
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Michael Ellerman authored
Follow the example of the cpu feature code, and add a mask of possible MMU features, MMU_FTRS_POSSIBLE. This is used in mmu_has_feature(), which allows the possible mask to act as a shortcut for any features that are not possible, but still allows the feature bit itself to be defined. We will use this in the next commit to allow MMU_FTR_RADIX checks to be elided when MMU_FTR_RADIX is not possible. Signed-off-by:
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- 01 May, 2016 8 commits
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Aneesh Kumar K.V authored
Core kernel doesn't track the page size of the VA range that we are invalidating. Hence we end up flushing TLB for the entire mm here. Later patches will improve this. We also don't flush page walk cache separetly instead use RIC=2 when flushing TLB, because we do a MMU gather flush after freeing page table. MMU_NO_CONTEXT is updated for hash. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
This file now contains both hash and radix specific code. Rename it to indicate this better. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
How we switch MMU context differs between hash and radix. For hash we need to switch the SLB details and for radix we need to switch the PID SPR. Signed-off-by:
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Aneesh Kumar K.V authored
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Aneesh Kumar K.V authored
For hash we create vmemmap mapping using bolted hash page table entries. For radix we fill the radix page table. The next patch will add the radix details for creating vmemmap mappings. Signed-off-by:
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Aneesh Kumar K.V authored
This adds routines for early setup for radix. We use device tree property "ibm,processor-radix-AP-encodings" to find supported page sizes. If we don't find the above we consider 64K and 4K as supported page sizes. We do map vmemap using 2M page size if we can. The linear mapping is done such that we use required page size for that range. For example memory of 3.5G is mapped such that we use 1G mapping till 3G range and use 2M mapping for the rest. Signed-off-by:
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