- 02 Sep, 2016 13 commits
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Christian König authored
As last resort try to evict BOs from the current working set into other memory domains. This effectively prevents command submission failures when VM page tables have been swapped out. v2: fix typos Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Christian König authored
All other errors can't be fixed by using a different memory domain. Signed-off-by:
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Alex Deucher authored
Normally on shutdown or reboot we don't care about necessarily making sure the hw is in a good state because the system is about to be powered down or reset. However, after a shutdown or reboot in a VM, it's best to tear down the hw properly otherwise there can be problems with the next VM use. Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Alex Deucher authored
Normally on shutdown or reboot we don't care about necessarily making sure the hw is in a good state because the system is about to be powered down or reset. However, after a shutdown or reboot in a VM, it's best to tear down the hw properly otherwise there can be problems with the next VM use. Reviewed-by:
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Alex Deucher authored
Close was not handled correctly. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Alex Deucher authored
Close was not handled correctly. Reviewed-by:
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Alex Deucher authored
Need to fix the error paths. Reviewed-by:
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Alex Deucher authored
Need to fix the error paths. Reviewed-by:
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Alex Deucher authored
Missed this case previously. No need to do anything if the device is already off. runtime pm will handle it. Acked-by:
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Alex Deucher authored
The sbios always powers up the dGPU on resume. Acked-by:
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Alex Deucher authored
Missed this case previously. No need to do anything if the device is already off. runtime pm will handle it. Acked-by:
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Alex Deucher authored
The sbios always powers up the dGPU on resume. Acked-by:
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Alex Deucher authored
The mqd is only used on CI and newer. Reviewed-by:
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- 31 Aug, 2016 22 commits
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Chunming Zhou authored
V2: a. gart recovery should be ahead of ring test. b. rename to amdgpu_ttm_recover_gart Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
V2: spin lock instead of mutex for gtt list Signed-off-by:
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Ken Wang authored
Acked-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
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Alex Deucher authored
Signed-off-by: -
Ken Wang authored
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Maruthi Srinivas Bayyavarapu authored
Signed-off-by:
Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by:
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Huang Rui authored
Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Maruthi Bayyavarapu authored
v2: corrected register offset shift v3: rebase fixes v4: fix firmware paths add SI smc firmware versions for sysfs dump remove unused function forward define fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field fix to miss adding thermal controller use vram_type instead of checking mem_gddr5 flag fix incorrect index of CG_FFCT_0 register fix incorrect reading method at si_get_current_pcie_speed Signed-off-by: -
Maruthi Srinivas Bayyavarapu authored
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Maruthi Srinivas Bayyavarapu authored
v2: renamed _atom_ to _atombios_ for consistency added ulClockParams to _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 and _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 to avoid build break Signed-off-by: -
Ken Wang authored
v3: guard doorbell_fini as well Reviewed-by:
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Ken Wang authored
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Ken Wang authored
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Huang Rui authored
This patch adds pcie port read/write entry, because it will be also used on si dpm part. Acked-by:
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Ken Wang authored
v5: rebase fixes v6: add mgcg arrays v7: rebase fixes v8: rebase fixes v9: add get_disabled_bios(), make get_xclk static v10: fix oland and hainan asic specific handle at si_program_aspm Signed-off-by:
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Ken Wang authored
v4: rebase fixes v5: use the generic nop fill v6: rebase fixes v7: rebase fixes copy count fixes from Jonathan general cleanup add fill buffer implementation v8: adapt write_pte and copy_pte to latest changes Signed-off-by: -
Ken Wang authored
v5: rebase fixes v6: rebase fixes v7: rebase fixes fix tile reg offset as noticed by Jonathan Drop some debugging remnants v8: add gfx v6 firmware versions for sysfs dump Acked-by: -
Ken Wang authored
v3: white space fixes Reviewed-by:
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Ken Wang authored
v4: rebase fixups v5: more fixes based on dce8 code v6: squash in dmif offset fix v7: rebase fixups v8: rebase fixups, drop some debugging remnants v9: fix BE build v10: include Marek's tiling fixes, add support for page_flip_target, set MASTER_UDPATE_MODE=0, fix cursor Acked-by: -
Ken Wang authored
v3: rebase fixups Reviewed-by:
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Ken Wang authored
v4: rebase fixups v5: rebase fixups v5: rebase fixups v6: rebase fixups for gart size changes v7: add gmc v6 firmware versions for sysfs dump Signed-off-by:
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Ken Wang authored
v4: drop unused DCE6 macro Acked-by:
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- 30 Aug, 2016 5 commits
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Ken Wang authored
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Monk Liu authored
sync switch buffer scheme with windows kmd for gfx v8, step1: append a switch_buffer to the end of CS v2:rebase on latest staging Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Jordan Lazare authored
If treating warnings as errors this causes a build error Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
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Tom St Denis authored
Only load the SDMA0/MEC1 firmware once in the Carrizo SMU manager driver. (v2) Avoid loading SDMA0 twice too. Signed-off-by:
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