- 22 Jan, 2014 38 commits
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Leonid Yegoshin authored
For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6132/
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Steven J. Hill authored
MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by:
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Leonid Yegoshin authored
New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by:
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Markos Chandras authored
The UNIQUE_ENTRYHI definition was duplicated whenever there was the need to flush the TLB entries. We move this common definition to a header file. Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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Markos Chandras authored
Add support for including VPE and TC ids in /proc/cpuinfo output as appropriate when MT/SMTC is enabled. Reviewed-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Leonid Yegoshin authored
Commit 225ae5fd "MIPS: Malta: Fix interupt number of CBUS UART" fixed the IRQ number for the ttyS2 CBUS UART. However, this now conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta interrupt code arbitrarily binds IPIs to INT2 and INT3 and since ttyS2 uses the INT2 IRQ line, closing the device disables the INT2 interrupt and this effectively disables the IPI1 interrupt as well. This patch is mainly a workaround until the Malta code is fixed properly. Signed-off-by:
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Leonid Yegoshin authored
The cacheer register is always implemented in the same way in the MIPS32r2 Imgtec cores so print the ES bit when an cache error occurs. Signed-off-by:
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Steven J. Hill authored
If GIC is present, then use it to send IPIs between the cores. Using GIC for IPIs is simpler and is usable for multicore systems compared to the existing way of doing IPIs where all VPEs had to be disabled for another VPE to access the Cause register in one of the TCs and enable all the VPEs back. Signed-off-by:
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Markos Chandras authored
According to Documentation/cpu-hotplug.txt, the cpu_present_mask should contain all the CPUs which are present in the system. Therefore, all the TCs currently present in the system should be marked as 'present' even if they will never be brought online. Signed-off-by:
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Markos Chandras authored
According to MIPS32 and MIPS64 PRA documents, a value of 7 in IL and DL fields is marked as "Reserved" so panic if the core uses this value in the config1 register. Also simplify the code a little bit. Signed-off-by:
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Markos Chandras authored
The mips_mt_* symbols are only built and exported if CONFIG_MIPS_MT is enabled. Fixes the following build problem when CONFIG_SMP is enabled but CONFIG_MIPS_MT is not. arch/mips/built-in.o: In function `cmp_prepare_cpus': arch/mips/kernel/smp-cmp.c:197: undefined reference to `mips_mt_set_cpuoptions' Signed-off-by:
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Ilia Mirkin authored
Fix nvram_read_alpha2 copying too many bytes over the ssb_sprom structure. Also fix the arguments of the read_macaddr, although the code was technically not wrong before due to an extra dereference. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by:
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Hauke Mehrtens authored
This adds support for vectored interrupt which is supported by the SoC using a MIPS 74K CPU like the BCM4716 and BCM4706. Signed-off-by:
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Hauke Mehrtens authored
The BCM47XX SoC code missed a cpu-feature-overrides.h header file, this patch adds it. This code supports a long line of SoCs with different features so for some features we still have to rely on the runtime detection. This was crated by checking the features of a BCM4712, BCM4704, BCM5354, BCM4716 and BCM4706 SoC and then tested on these SoCs. There are some SoCs missing but I hope they do not have any more or less features. Signed-off-by:
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Hauke Mehrtens authored
Move the possible nvram sizes from the stack into the data segment Signed-off-by:
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Hauke Mehrtens authored
plat_irq_dispatch() is called from asm code, add asmlinkage. Signed-off-by:
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Hauke Mehrtens authored
The defconfig for bcm47xx contained lots of driver which are not special for these SoCs and missed on the other side some some drivers for parts essential for these SoC and only found on here. The flash, usb and some Ethernet driver were missing. Signed-off-by:
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Hauke Mehrtens authored
The BCM47xx SoCs have a 8250 serial compatible console at address 0x18000300 and an other at 0x18000400. On most devices 0x18000300 is wired to some pins on the board, we should use that. This is the smae for the AI (bcma) and the SB (ssb) bus, this is some offset on the chip common core. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
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Hauke Mehrtens authored
bcm47xx only uses the CFE code for early print to a console, but that is also possible with a early print serial 8250 driver. The CFE api init causes hangs somewhere in prom_init_cfe() on some devices like the Buffalo WHR-HP-G54 and the Asus WL-520GU. This was reported in https://dev.openwrt.org/ticket/4061 and https://forum.openwrt.org/viewtopic.php?id=17063 This will remove all the CFE handling code from bcm47xx. Signed-off-by:
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Hauke Mehrtens authored
Recently the output of "system type" in /proc/cpuinfo was changed to Broadcom BCM4730 (Some sample board), but it is better to just print the SoC name in the "system type" entry. The board name will be added in the machine entry later. Signed-off-by:
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Jonas Gorski authored
All MIPS cores on BCM63XX identify as Broadcom, not MIPS, so no need to support non-broadcom MIPS CPUs. This also ensures that CPU_BMIPS is always selected. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Signed-off-by:
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Jonas Gorski authored
BMIPS32 and BMIPS3300 also need to be available for MIPS32R1, as bcm47xx might not select BMIPS. Signed-off-by:
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Jonas Gorski authored
Let BCM47XX_SSB select the appropriate BMIPS CPUs enountered on those systems. Signed-off-by:
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Jonas Gorski authored
Let each supported chip select the appropirate SYS_HAS_CPU_BMIPS* option for its embedded processor, so support will be conditionally included. Signed-off-by:
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Jonas Gorski authored
Use the return value for guarding further SMP setup. Signed-off-by:
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Jonas Gorski authored
Add a helper similar to the generic register_XXX_smp_ops() for bmips. Register SMP UP ops in case of BMIPS32/3300. Signed-off-by:
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Jonas Gorski authored
Codewise there is no difference between these two, so it does not make sense to treat them differently. Also chip families having one of these tend to have the other. Signed-off-by:
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Jonas Gorski authored
As they are MIPS32 CPUs they do support the prefetch opcode. Signed-off-by:
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Jonas Gorski authored
All BMIPS CPUs support HIGHMEM, so it should be selected by CPU_BMIPS. Signed-off-by:
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Jonas Gorski authored
Instead of treating each flavour as an exclusive CPU to select, make BMIPS the only option and let SYS_HAS_CPU_BMIPS* decide for which flavours to include support. Run tested on BMIPS3300 and BMIPS4350, only build tested for BMIPS4380 and BMIPS5000. Signed-off-by:
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Jonas Gorski authored
Allow building for all bmips cpus at the same time by changing ifdefs to checks for the cpu type, or adding appropriate checks to the assembly. Since BMIPS43XX and BMIPS5000 require different IPI implementations, split the SMP ops into one for each, so the runtime overhead is only at registration time for them. Signed-off-by:
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Jonas Gorski authored
Add guards around the enum to allow including cpu.h from assembly. Signed-off-by:
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Jonas Gorski authored
BCM3368 has the same shared TLB as BCM6358. Signed-off-by:
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Jonas Gorski authored
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Jonas Gorski authored
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Jonas Gorski authored
Properly set up the HSSPI clock rate depending on the SoC's PLL rate. Signed-off-by:
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Jonas Gorski authored
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- 13 Jan, 2014 2 commits
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Paul Burton authored
CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
These macros are not used anywhere in the kernel. Remove them. Signed-off-by:
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