- 06 May, 2015 1 commit
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Gregory CLEMENT authored
commit 548ae94c upstream. On Armada 38x SoCs, under heavy I/O load, the system hangs when CPU Idle is enabled. Waiting for a solution to this issue, this patch disables the CPU Idle support for this SoC. As CPU Hot plug support also uses some of the CPU Idle functions it is also affected by the same issue. This patch disables it also for the Armada 38x SoCs. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 19 Feb, 2015 1 commit
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Uwe Kleine-König authored
of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs in arch/arm as const, too. While at it also add some __initconst annotations. Acked-by:
Jason Cooper <jason@lakedameon.net> Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 04 Dec, 2014 1 commit
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Thomas Petazzoni authored
This commit adjusts the registration of the cpufreq-dt driver in the mvebu platform to indicate to the cpufreq driver that the platform has independent clocks for each CPU. Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Signed-off-by:
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- 22 Nov, 2014 2 commits
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Gregory CLEMENT authored
This commit implements the CPU hotplug support for the Marvell Armada 38x platform. Similarly to what was done for the Armada XP, this commit: * Implements the ->cpu_die() function of SMP operations by calling armada_38x_do_cpu_suspend() to enter the deep idle state for CPUs going offline. * Implements a dummy ->cpu_kill() function, simply needed for the kernel to know we have CPU hotplug support. * The mvebu_cortex_a9_boot_secondary() function makes sure to wake up the CPU if waiting in deep idle state by sending an IPI before deasserting the CPUs from reset. This is because mvebu_cortex_a9_boot_secondary() is now used in two different situations: for the initial boot of secondary CPUs (where CPU reset deassert is used to wake up CPUs) and for CPU hotplug (where an IPI is used to take CPU out of deep idle). * At boot time, we exit from the idle state in the ->smp_secondary_init() hook. This commit has been tested using CPU hotplug through sysfs (/sys/devices/system/cpu/cpuX/online) and using kexec. Signed-off-by: -
Gregory CLEMENT authored
This patch removes the unneeded include of the armada-370-xp.h header. It also moves some declarations from this file into more accurate places. Finally, it also adds a comment explaining that we can't remove yet the smp field in the dt machine struct due to backward compatibly of the device tree. In a few releases, when the old device tree will be obsolete, we will be able to remove the smp field and then the armada-370-xp.h header. Signed-off-by:
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- 03 Oct, 2014 1 commit
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Viresh Kumar authored
The naming convention of this driver was always under the scanner, people complained that it should have a more generic name than cpu0, as it manages all CPUs that are sharing clock lines. Also, in future it will be modified to support any number of clusters with separate clock/voltage lines. Lets rename it to 'cpufreq_dt' from 'cpufreq_cpu0'. Tested-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 24 Jul, 2014 10 commits
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Gregory CLEMENT authored
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9 core. Consequently, the procedure to enter the idle state is different: interaction with the SCU, not disabling snooping, etc. Signed-off-by:
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Gregory CLEMENT authored
This commit introduces the cpuidle support for Armada 370. The main difference compared to the already supported Armada XP is that the Armada 370 has an issue caused by "a slow exit process from the deep idle state due to heavy L1/L2 cache cleanup operations performed by the BootROM software" (cf errata GL-BootROM-10). To work around this issue, we replace the restart code of the BootROM by some custom code located in an internal SRAM. For this purpose, we use the common function mvebu_boot_addr_wa() introduced in the commit "ARM: mvebu: Add a common function for the boot address work around". The message in case of failure to suspend the system was switched from the warn level to the debug level. Indeed due to the "slow exit process from the deep idle state" in Armada 370, this situation happens quite often. Using the debug level avoids spamming the kernel logs, but still allows to enable it if needed. Signed-off-by:
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Gregory CLEMENT authored
This driver will be able to manage the cpuidle for more SoCs than just Armada 370 and XP. It will also support Armada 38x and potentially other SoC of the Marvell Armada EBU family. To take this into account, this patch renames the driver and its symbols. It also changes the driver name from cpuidle-armada-370-xp to cpuidle-armada-xp, because separate platform drivers will be registered for the other SoC types. This change must be done simultaneously in the cpuidle driver and in the PMSU code in order to remain bisectable. Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/1406120453-29291-12-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by:
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Gregory CLEMENT authored
On some mvebu v7 SoCs (the ones using a Cortex-A9 core and not a PJ4B core), the snoop disabling feature does not exist as the hardware coherency is handled in a different way. Therefore, in preparation to the introduction of the cpuidle support for those SoCs, this commit modifies the mvebu_v7_psmu_idle_prepare() function to take several flags, which allow to decide whether snooping should be disabled, and whether we should use the deep idle mode or not. Signed-off-by:
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Gregory CLEMENT authored
The resume address used by the cpuidle code will not always be the same depending on the SoC. Using a local variable to store the resume address allows to keep the same function for the PM notifier but with a different address. This address will be set during the initialization of the cpuidle logic in pmsu.c. Signed-off-by:
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Gregory CLEMENT authored
In preparation to the addition of the cpuidle support for more SoCs, this patch moves the Armada XP specific initialization to a separate function. Signed-off-by:
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Gregory CLEMENT authored
Most of the function related to the PMSU are not specific to the Armada 370 or Armada XP SoCs. They can also be used for most of the other mvebu ARMv7 SoCs, and will actually be used to support cpuidle on Armada 38x. Signed-off-by:
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Gregory CLEMENT authored
On some of the mvebu SoCs and due to internal BootROM issue, the CPU initial jump code must be placed in the SRAM memory of the SoC. In order to achieve this, we have to unmap the BootROM and at some specific location where the BootROM was placed, create a dedicated MBus window for the SRAM. This SRAM is initialized with a few instructions of code that allows to jump to the real secondary CPU boot address. The SRAM used is the Crypto engine one. This work around is currently needed for booting SMP on Armada 375 Z1 and will be needed for cpuidle support on Armada 370. Instead of duplicating the same code, this commit introduces a common function to handle it: mvebu_setup_boot_addr_wa(). Signed-off-by:
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Gregory CLEMENT authored
Sorting the headers in alphabetic order will help to reduce conflicts when adding new headers later. Signed-off-by:
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Gregory CLEMENT authored
do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(), have been merged into a single function called armada_370_xp_pmsu_idle_enter() by the commit "bbb92284 ARM: mvebu: slightly refactor/rename PMSU idle related functions", in prepare for the introduction of the CPU hotplug support for Armada XP. But for cpuidle the prepare function will be common to all the mvebu SoCs that use the PMSU, while the suspend function will be specific to each SoC. Keeping the prepare function separate will help reducing code duplication while new SoC support is added. Signed-off-by:
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- 23 Jul, 2014 1 commit
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Wei Yongjun authored
In case of error, the function clk_get() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Link: https://lkml.kernel.org/r/1406038688-26417-1-git-send-email-weiyj_lk@163.com Signed-off-by:
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- 16 Jul, 2014 1 commit
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Thomas Petazzoni authored
This commit adds the necessary code in the Marvell EBU PMSU driver to support dynamic frequency scaling. In essence, what this new code does is that it: * registers the frequency operating points supported by the CPU; * registers a clock notifier of the CPU clocks. The notifier function listens to the newly introduced APPLY_RATE_CHANGE event, and uses that to finalize the frequency transition by doing the part of the procedure that involves the PMSU; * registers a platform device for the cpufreq-generic driver, which will take care of the CPU frequency transitions. Signed-off-by:
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- 08 Jul, 2014 1 commit
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Gregory CLEMENT authored
In the inline asm part of the function armada_370_xp_pmsu_idle_enter() the input operand was used. The intent here was to let the compiler choose this register so it could do the optimization it needed. However an input operand is not supposed to be modified by the inline asm code. This can lead to improper generated instructions. In some case generated instruction the compiler made the choice to reuse the same register to store the return value. But in the assembly part this register was modified, so it can lead to return an wrong value. The fix is to use a clobber. Thanks to this the compiler will know that the value of this register will be modified. Signed-off-by:
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- 30 Jun, 2014 2 commits
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Thomas Petazzoni authored
On Marvell Armada XP, when a CPU comes back from deep idle state of cpuidle, it restarts its execution at armada_370_xp_cpu_resume(), which puts back the CPU into the coherency, and then calls the generic cpu_resume() function. While this works on little-endian configurations, it doesn't work on big-endian configurations because the CPU restarts in little-endian, and therefore must be switched back to big-endian to operate properly. To achieve this, a 'setend be' instruction must be executed in big-endian configurations. However, the ARM_BE8() macro that is used to implement nice compile-time conditional for ARM LE vs. ARM BE8 is not easily usable in inline assembly. Therefore, this patch moves the armada_370_xp_cpu_resume() C function, which was anyway just a block of inline assembly, into a proper pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be) instruction. Without this patch, an Armada XP big endian configuration with cpuidle enabled fails to boot, as it hangs as soon as one of the CPU hits the deep idle state. Signed-off-by:
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Sachin Kamat authored
'armada_370_xp_cpu_pm_init' is local to this file. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Link: https://lkml.kernel.org/r/1403610235-22654-3-git-send-email-sachin.kamat@samsung.com Signed-off-by:
Sachin Kamat <sachin.kamat@samsung.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
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- 21 Jun, 2014 2 commits
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Thomas Petazzoni authored
The PMSU idle enter/exit functions will be needed for the CPU hotplug implementation on Armada XP, so this commit removes their static qualifier, and adds the appropriate prototypes in armada-370-xp.h. Signed-off-by:
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Thomas Petazzoni authored
The CPU hotplug code will need to call into PMSU functions to enter and exit from deep idle states. However, the deep idle state is currently entered by a function called do_armada_370_xp_cpu_suspend() whose name really suggests it's an internal function, but we need to export it to other files in mach-mvebu. Therefore, this commit: * Merges the code of do_armada_370_xp_cpu_suspend() into armada_370_xp_pmsu_idle_prepare(), into a single function called armada_370_xp_pmsu_idle_enter(), which prepares the PMSU for deep idle, and then enters the deep idle state. This code will be common to both cpuidle and CPU hotplug. * For symetry, it renames the armada_370_xp_pmsu_idle_restore() function to armada_370_xp_pmsu_idle_exit(). We also remove the 'noinline' qualifier for these functions, which apparently had no reason to be here. Signed-off-by:
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- 20 Jun, 2014 1 commit
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Thomas Petazzoni authored
The armada_370_xp_pmsu_idle_prepare() function is only used internally to pmsu.c, so there's no reason to not use the static qualifier. Signed-off-by:
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- 08 May, 2014 6 commits
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Gregory CLEMENT authored
The cpuidle is a platform driver so we register the device just after the initialization of the board in an arch_initcall. Signed-off-by:
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Gregory CLEMENT authored
In order to have well encapsulated code, we use notifier callbacks for CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code. Signed-off-by:
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Gregory CLEMENT authored
The cpu idle support will need to access to Power Management Service Unit. This commit adds the architecture related functions that will be used in the idle path of the cpuidle driver. Signed-off-by:
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Gregory CLEMENT authored
This commit adds a function which adjusts the PMSU configuration to automatically power down the L2 and coherency fabric when we enter a certain idle state. This feature is part of the Power Management Service Unit of the Armada 370 and Armada XP SoCs. Signed-off-by:
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Thomas Petazzoni authored
Since the Armada 38x PMSU registers are slightly different than the Armada 370/XP PMSU ones, we introduce a new compatible string "armada-380-pmsu" in the PMSU driver. These differences are not visible for the current usage of the PMSU, but they might become visible in the future. Signed-off-by:
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Thomas Petazzoni authored
The pmsu.c driver contained an armada_xp_boot_cpu() function that sets the boot address of a secondary CPUs and deasserts the reset. However, the Armada 375 needs a slightly different logic, so it makes more sense to move this code into the Armada XP specific platsmp.c. In order to achieve this, the mvebu_pmsu_set_cpu_boot_addr() function is exported. It will be needed for both the Armada XP and Armada 38x SMP implementations. Signed-off-by:
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- 24 Apr, 2014 4 commits
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Gregory CLEMENT authored
Setting the start (or boot) address of a CPU is no more used only during SMP bring up on Armada 370/XP, but it will also be used by the CPU idle function of Armada XP, and by the Armada 38x SMP support. Therefore this commit creates a separate PMSU function to set the boot address of a CPU with the PMSU. Signed-off-by:
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Gregory CLEMENT authored
The initial binding for PMSU was wrong, as it didn't take into account all the registers from the PMSU and moreover it referred to the CPU reset registers which are not part of PMSU. The Power Management Unit Service block also controls the Coherency Fabric subsystem. These registers are needed for the CPU idle implementation for the Armada 370/XP, it allows to enter a deep CPU idle state where the Coherency Fabric and the L2 cache are powered down. This commit adds support for a new compatible for the PMSU node which includes the registers related to the coherency fabric. It also keeps compatibility with the old compatible string. Signed-off-by:
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Thomas Petazzoni authored
Until now, the PMSU driver was using of_iomap() to map its registers, but of_iomap() doesn't call request_mem_region(). This commit fixes the memory mapping code of the PMSU to do so, which will also be useful for a later commit since we will need to adjust the resource base address and size for Device Tree backward compatibility. Signed-off-by:
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Thomas Petazzoni authored
This commit changes the PMSU driver to no longer map itself the CPU reset registers, and instead call into the CPU reset driver to deassert the secondary CPUs for SMP booting. In order to provide Device Tree backward compatibility, the CPU reset driver is extended to not only support its official compatible string "marvell,armada-370-cpu-reset", but to also look at the PMSU compatible string "marvell,armada-370-xp-pmsu" to find the CPU reset registers address. This allows old Device Tree to work correctly with newer kernel versions. Therefore, the CPU reset driver implements the following logic: * If one of the normal compatible strings "marvell,armada-370-cpu-reset" is found, then we map its first memory resource as the CPU reset registers. * Otherwise, if none of the normal compatible strings have been found, we look for the "marvell,armada-370-xp-pmsu" compatible string, and we map the second memory as the CPU reset registers. Signed-off-by:
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- 24 Nov, 2013 1 commit
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Jisheng Zhang authored
This patch fixes conflicting types for 'set_cpu_coherent' and fixes the following sparse warnings. arch/arm/mach-mvebu/system-controller.c:42:38: warning: symbol 'armada_370_xp_system_controller' was not declared. Should it be static? arch/arm/mach-mvebu/system-controller.c:49:38: warning: symbol 'orion_system_controller' was not declared. Should it be static? arch/arm/mach-mvebu/system-controller.c:67:6: warning: symbol 'mvebu_restart' was not declared. Should it be static? arch/arm/mach-mvebu/coherency.c:31:15: warning: symbol 'coherency_phys_base' was not declared. Should it be static? arch/arm/mach-mvebu/coherency.c:48:5: warning: symbol 'set_cpu_coherent' was not declared. Should it be static? arch/arm/mach-mvebu/coherency.c:123:12: warning: symbol 'coherency_init' was not declared. Should it be static? arch/arm/mach-mvebu/pmsu.c:38:5: warning: symbol 'armada_xp_boot_cpu' was not declared. Should it be static? arch/arm/mach-mvebu/pmsu.c:61:12: warning: symbol 'armada_370_xp_pmsu_init' was not declared. Should it be static? arch/arm/mach-mvebu/platsmp.c:49:13: warning: symbol 'set_secondary_cpus_clock' was not declared. Should it be static? arch/arm/mach-mvebu/platsmp.c:97:13: warning: symbol 'armada_xp_smp_prepare_cpus' was not declared. Should it be static? arch/arm/mach-mvebu/hotplug.c:24:12: warning: symbol 'armada_xp_cpu_die' was not declared. Should it be static? Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Acked-by:
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- 18 Sep, 2013 1 commit
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Jisheng Zhang authored
Add of_node_put to properly decrement the refcount when we are done using a given node. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
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- 21 Nov, 2012 1 commit
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Gregory CLEMENT authored
The Armada 370 and Armada XP SOCs have a power management service unit which is responsible for powering down and waking up CPUs and other SOC units. This patch adds support for this unit. Signed-off-by:
Yehuda Yitschak <yehuday@marvell.com> Signed-off-by:
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