- 19 Jun, 2019 2 commits
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Bjorn Andersson authored
Enable SMMUs on 8996 now that the WRZ workaround in the arm-smmu driver has landed. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Andy Gross <agross@kernel.org>
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Bjorn Andersson authored
The domain specifier was changed from using "reg" to "qcom,apr-domain", update the dts accordingly. Acked-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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- 18 Jun, 2019 3 commits
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Bjorn Andersson authored
This adds an initial dts for the Dragonboard 845. Supported functionality includes Debug UART, UFS, USB-C (peripheral), USB-A (host), microSD-card and Bluetooth. Initializing the SMMU is clearing the mapping used for the splash screen framebuffer, which causes the board to reboot. This can be worked around using: fastboot oem select-display-panel none Reviewed-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by:
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Bjorn Andersson authored
Enable the PCIe PHY and controller found on the QCS404 EVB. Signed-off-by: -
Bjorn Andersson authored
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, define these to for the platform. Reviewed-by:
Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by:
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- 17 Jun, 2019 2 commits
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Marc Gonzalez authored
Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes. Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537Signed-off-by:
Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by:
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Marc Gonzalez authored
The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB. (*) Aggregate Network-on-Chip #1 Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18Signed-off-by:
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- 12 Jun, 2019 5 commits
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Bjorn Andersson authored
MDSS and its friends complain about the DTS is using legacy clock names, update these to silence the warnings. Reviewed-by:
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Niklas Cassel authored
The current entry-latency-us is too short. The proper way to convert between the device tree properties from the vendor tree to the upstream PSCI device tree properties is: entry-latency-us = qcom,time-overhead - qcom,latency-us which gives entry-latency-us = 210 - 80 = 130 Fixes: f6aee7af ("arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states") Signed-off-by:
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Amit Kucheria authored
Add device bindings for cpuidle states for cpu devices. [marc: rebase, fix arm,psci-suspend-param, fix entry-latency-us] Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by:
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Sibi Sankar authored
This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Sibi Sankar <sibis@codeaurora.org> Signed-off-by:
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Bjorn Andersson authored
The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Tested-by:
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- 09 Jun, 2019 2 commits
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Andy Gross authored
This patch adds a reset-cells property to the gcc controller on the QCS404. Without this in place, we get warnings like the following if nodes reference a gcc reset: arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 DTC arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 Signed-off-by: -
Leo Yan authored
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel, so can dismiss warning during initialisation. Cc: Andy Gross <agross@kernel.org> Cc: David Brown <david.brown@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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- 30 May, 2019 23 commits
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Sibi Sankar authored
Add the rpmpd node on the msm8998 and define the available levels. Reviewed-by:
Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by:
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Bjorn Andersson authored
Add the rpmpd node on the qcs404 and define the available levels. Reviewed-by:
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Bjorn Andersson authored
Although we don't describe lpass and wcss with all the details needed to control them in a Trustzone-less environment, move them under soc in order to tidy up the structure and prepare for describing them fully. Reviewed-by:
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Bjorn Andersson authored
Add all the properties needed to describe the CDSP for both the Trustzone and non-Trustzone based remoteproc case, allowing any child devices to be described once by just overriding the compatible to match the firmware available on the board. Reviewed-by:
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Bjorn Andersson authored
The bus halt registers in TCSR are referenced as a syscon device, add these so that we can reference them from the remoteproc nodes. Reviewed-by:
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Bjorn Andersson authored
With the Trustzone based CDSP remoteproc driver these clocks are controlled elsewhere and as they are not enabled by anything in Linux the clock framework will turn them off during lateinit. This results in issues either to later start the CDSP, using the Trustzone interface, or if the CDSP is already running it will crash. Reviewed-by:
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Raju P.L.S.S.S.N authored
Add device bindings for cpuidle states for cpu devices. Cc: <mkshah@codeaurora.org> Acked-by:
Evan Green <evgreen@chromium.org> Signed-off-by:
Raju P.L.S.S.S.N <rplsssn@codeaurora.org> [amit: rename the idle-states to more generic names and fixups] Signed-off-by:
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Amit Kucheria authored
msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Add capacity-dmips-mhz property to allow the topology code to determine the actual capacity by taking into account the highest frequency for each CPU. Acked-by:
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Amit Kucheria authored
Add device bindings for cpuidle states for cpu devices. msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Acked-by:
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Amit Kucheria authored
Instead of using Qualcomm-specific terminology, use generic node names for the idle states that are easier to understand. Move the description into the "idle-state-name" property. Acked-by:
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Amit Kucheria authored
The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Acked-by:
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Bjorn Andersson authored
Add a node describing the Turing Clock Controller of the QCS404. Given the default access restriction the node is left disabled. Reviewed-by:
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Niklas Cassel authored
Add device bindings for cpuidle states for cpu devices. Acked-by:
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Jordan Crouse authored
Some Adreno GPU targets require a special zap shader to bring the GPU out of secure mode. Define a region to allocate and store the zap shader. Signed-off-by:
Jordan Crouse <jcrouse@codeaurora.org> [bjorn: Rebase ontop of recent reserved-memory patch] Signed-off-by:
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Jordan Crouse authored
Add the nodes to describe the Adreno GPU and GMU devices for sdm845. Reviewed-by:
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Bjorn Andersson authored
The MTP is a "mobile reference device", as such the default operation is to use fastboot to boot/flash software onto it and the common case is thereby that we boot with a USB cable connected downstream from a PC or a hub. And without support for the PMI8998 charger block VBUS will not be driven by the device. Switch to peripheral until we can enable OTG. Reviewed-by:
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by:
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Niklas Cassel authored
Increase s3 max voltage in accordance to QCS404 CPR Fusing Guide Rev 6.0 Signed-off-by:
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Niklas Cassel authored
The current l3 min voltage level is not supported by the regulator (the voltage is not a multiple of the regulator step size), so a driver requesting this exact voltage would fail, see discussion in: https://patchwork.kernel.org/comment/22461199/ It was agreed upon to set a min voltage level that is a multiple of the regulator step size. There was actually a patch sent that did this: https://patchwork.kernel.org/patch/10819313/ However, the commit 331ab98f ("arm64: dts: qcom: qcs404: Fix voltages l3") that was applied is not identical to that patch. Signed-off-by:
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Amit Kucheria authored
The adc outputs shouldn't contain information about their configuration e.g. 100K pull-up, but just reflect the name of the signal in the schematics. Making them labels also allows us to overwrite their configuration in board-specific DTs. Sort them by order as used in adc5_chans_rev2, while we're at it. Signed-off-by:
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Amit Kucheria authored
Set the qcom,ratiometric property to make the VADC use the VDD reference (1.875V) and GND for channel calibration of the temperature channels instead of 1.25V. Allow a 200us delay between the AMUX configuration and ADC starting conversion using qcom,hw-settle-time as described in documentation. Fixes: 041b9a7b ("arm64: dts: pms405: Export PMIC temperature to thermal framework") Signed-off-by:
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Amit Kucheria authored
SDM845 implements ARM's Dynamiq architecture that allows the big and LITTLE cores to exist in a single cluster sharing the L3 cache. Fix the cpu-map to put all cpus into a single cluster. Reviewed-by:
Sudeep Holla <sudeep.holla@arm.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Vinod Koul authored
Fix the typo "dreive-strength" and use correct property drive-strength Fixes: 7241ab94 ("arm64: dts: qcom: qcs404: Add sdcc1 node") Signed-off-by:
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Evan Green authored
Add the reset controller for the UFS controller, and wire it up so that the UFS PHY can initialize itself without relying on implicit sequencing between the two drivers. Reviewed-by:
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- 19 May, 2019 3 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifsLinus Torvalds authored
Pull UBIFS fixes from Richard Weinberger: - build errors wrt xattrs - mismerge which lead to a wrong Kconfig ifdef - missing endianness conversion * tag 'upstream-5.2-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubifs: Convert xattr inum to host order ubifs: Use correct config name for encryption ubifs: Fix build error without CONFIG_UBIFS_FS_XATTR
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Linus Torvalds authored
Merge yet more updates from Andrew Morton: "A few final bits: - large changes to vmalloc, yielding large performance benefits - tweak the console-flush-on-panic code - a few fixes" * emailed patches from Andrew Morton <akpm@linux-foundation.org>: panic: add an option to replay all the printk message in buffer initramfs: don't free a non-existent initrd fs/writeback.c: use rcu_barrier() to wait for inflight wb switches going into workqueue when umount mm/compaction.c: correct zone boundary handling when isolating pages from a pageblock mm/vmap: add DEBUG_AUGMENT_LOWEST_MATCH_CHECK macro mm/vmap: add DEBUG_AUGMENT_PROPAGATE_CHECK macro mm/vmalloc.c: keep track of free blocks for vmap allocation
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