- 04 Sep, 2017 23 commits
-
-
Paul Burton authored
In preparation for removing the gic_present global variable, switch to using the mips_gic_present() function instead. For the most part this is a straightforward substitution. In cases which previously wrapped the GIC case in an #ifdef CONFIG_MIPS_GIC that #ifdef has been removed, since mips_gic_present() will return a compile-time constant false allowing the affected code to be optimised out anyway. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17044/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
-
Paul Burton authored
All in-tree platforms now probe the GIC driver using device tree, and as such nothing calls gic_init() any longer. Remove the dead code. Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17043/Signed-off-by:
-
Paul Burton authored
We provide a forward declaration of the __gic_irq_dispatch() function for no apparent reason. Remove it. Signed-off-by:
-
Paul Burton authored
The MIPS VDSO code is no longer reliant upon the irqchip driver to provide the address of the GIC's user-visible section via gic_get_usm_range(). Remove the now-dead code. Signed-off-by:
-
Paul Burton authored
We don't really need gic_get_usm_range() to abstract discovery of the address of the GIC user-visible section now that we have access to its base address globally. Switch to calculating it ourselves, which will allow us to stop requiring the irqchip driver to care about a counter exposed to userland for use via the VDSO. Signed-off-by:
-
Paul Burton authored
Move the definitions of macros used to convert between hardware IRQ numbers & shared or local interrupt numbers into the irqchip driver, which is all that should ever need to care about them. Remove GIC_CPU_TO_VEC_OFFSET() in the process since it's never used. Signed-off-by:
-
Paul Burton authored
The GIC_CPU_INT* macros are never used. Remove the dead code. Signed-off-by:
-
Paul Burton authored
Move the definition of VP-local interrupts provided by the MIPS Global Interrupt Controller to the new asm/mips-gic.h header to be alongside the new accessor functions. Whilst at it, convert to an enum which lends itself more easily to expansion & documentation. Signed-off-by:
-
Paul Burton authored
Convert the remaining accesses to registers in the GIC VP-local & VP-other register blocks to use the new accessor functions provided by asm/mips-gic.h, resulting in code which is often shorter & easier to read. Signed-off-by:
-
Paul Burton authored
Use the new accessor functions provided by asm/mips-gic.h to access masks controlling local interrupts, resulting in code which is often shorter & easier to read. Signed-off-by:
-
Paul Burton authored
Convert the remaining accesses to registers in the GIC shared register block to use the new accessor functions provided by asm/mips-gic.h, resulting in code which is often shorter & easier to read. Signed-off-by:
-
Paul Burton authored
Remove the gic_map_to_vpe() function in favour of using the new write_gic_map_vp() accessor function which isn't any more complex to use & allows us to drop a level of abstraction. Signed-off-by:
-
Paul Burton authored
Remove the gic_map_to_pin() function in favour of using the new write_gic_map_pin() accessor function which isn't any more complex to use & allows us to drop a level of abstraction. Signed-off-by:
-
Paul Burton authored
Remove the gic_set_dual_edge() function in favour of using the new change_gic_dual() accessor function which provides equivalent functionality. This also allows us to remove the gic_update_bits() function which gic_set_dual_edge() was the last user of, along with the GIC_INTR_OFS() & GIC_INTR_BIT() macros. Signed-off-by:
-
Paul Burton authored
Remove the gic_set_trigger() function in favour of using the new change_gic_trig() accessor function which provides equivalent functionality. Signed-off-by:
-
Paul Burton authored
Remove the gic_set_polarity() function in favour of using the new change_gic_pol() accessor function which provides equivalent functionality. Signed-off-by:
-
Paul Burton authored
The gic_set_mask() & gic_reset_mask() functions are now no more convenient to call than the write_gic_smask() or write_gic_rmask() accessor functions. Remove the layer of abstraction. Signed-off-by:
-
Paul Burton authored
Simplify gic_local_irq_domain_map() by: - Moving the check for invalid IRQs outside of the loop. - Moving the decision about whether to use gic_cpu_pin or timer_cpu_pin outside of the loop. - Using the new write_gic_vo_map() accessor function to avoid the need to handle each map register separately. Signed-off-by:
-
Paul Burton authored
Simplify the reads of the bitmaps indicating pending & masked interrupts in gic_handle_shared_int() using the __ioread32_copy() & __ioread64_copy() helper functions. Signed-off-by:
-
Paul Burton authored
We currently have __ioread32_copy, __iowrite32_copy & __iowrite64_copy helpers in lib/iomap_copy.c. This patch adds __ioread64_copy to round out the set, allowing copies from I/O memory using 32 or 64 bit reads. [ralf@linux-mips.org: Changed to move all the code of this patch to be applied to arch/mips temporarily.] Signed-off-by:
-
Paul Burton authored
Nothing needs gic_read_local_vp_id() any longer, so remove the dead code. Signed-off-by:
-
Paul Burton authored
Rather than calling the gic_read_local_vp_id() function from the GIC irqchip driver, call read_gic_vl_ident() to read the GIC_VL_IDENT register directly. This will allow us to remove gic_read_local_vp_id() from the irqchip driver in a further patch, since that driver doesn't actually care about the register's value. Signed-off-by:
-
Paul Burton authored
The MIPS GIC clocksource driver is no longer using the accessor functions provided by the irqchip driver, so remove them. Signed-off-by:
-
- 01 Sep, 2017 1 commit
-
-
Paul Burton authored
Use the accessor functions provided by asm/mips-gic.h rather than calling functions provided by the GIC irqchip driver, in preparation for those non-IRQ-related functions being removed from the irqchip driver. Signed-off-by:
-
- 30 Aug, 2017 3 commits
-
-
Paul Burton authored
Switch from calling functions exported by the GIC interrupt controller to using new accessors provided by asm/mips-gic.h. This will allow the counter-handling functionality to be removed from the interrupt controller driver, where it doesn't really belong, and also allow for inlining of the accesses to the GIC. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17021/Signed-off-by:
-
Paul Burton authored
This patch introduces a new header providing accessor functions for the MIPS Global Interrupt Controller (GIC) mirroring those provided for the other 2 components of the MIPS Coherent Processing System (CPS) - the Coherence Manager (CM) & Cluster Power Controller (CPC). This header makes use of the new standardised CPS accessor macros where possible, but does require some custom accessors for cases where we have either a bit or a register per interrupt. A major advantage of this over the existing include/linux/irqchip/mips-gic.h definitions is that code performing accesses can become much simpler, for example this: gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), (unsigned long)trig << GIC_INTR_BIT(intr)); ...can become simply: change_gic_trig(intr, trig); The accessors handle 32 vs 64 bit in the same way as for CM & CPC code, which means that GIC code will also not need to worry about the access size in most cases. They are also accessible outside of drivers/irqchip/irq-mips-gic.c which will allow for simplification in the use of the non-interrupt portions of the GIC (eg. counters) which currently require the interrupt controller driver to expose helper functions for access. This patch doesn't change any existing code over to use the new accessors yet, since a wholesale change would be invasive & difficult to review. Instead follow-on patches will convert code piecemeal to use this new header. The one change to existing code is to rename gic_base to mips_gic_base & make it global, in order to fit in with the naming expected by the standardised CPS accessor macros. Signed-off-by: -
James Hogan authored
A SYNC is required between enabling the GIC region and actually trying to use it, even if the first access is a read, otherwise its possible depending on the timing (and in my case depending on the precise alignment of certain kernel code) to hit CM bus errors on that first access. Add the SYNC straight after setting the GIC base. [paul.burton@imgtec.com: Changes later in this series increase our likelihood of hitting this by reducing the amount of code that runs between enabling the GIC & accessing it.] Fixes: a7057270 ("irqchip: mips-gic: Add device-tree support") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
-
- 29 Aug, 2017 13 commits
-
-
Christoph Hellwig authored
The floppy drivers doesn't otherwise use the DMA API, so indirecting through it just for cache flushing in MIPS-specific code just call dma_cache_wback_inv directly. Signed-off-by:
Christoph Hellwig <hch@lst.de> Cc: iommu@lists.linux-foundation.org Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Michal Simek <monstr@monstr.eu> Cc: David Howells <dhowells@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: x86@kernel.org Cc: linux-mips@linux-mips.org Cc: linux-ia64@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-xtensa@linux-xtensa.org Cc: linux-sh@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17183/Signed-off-by:
-
Paul Burton authored
In generic_defconfig set CONFIG_NR_CPUS to 16 rather than 2, which is a rather too low limit for many modern day MIPS systems. Signed-off-by:
-
Paul Burton authored
Leave CONFIG_USB_SUPPORT at its default, allowing board config fragments to make use of USB drivers without needing to override it & trigger warnings from merge_config.sh. Signed-off-by:
-
Paul Burton authored
On systems that support MT ASE multithreading (ie. VPEs) we are very likely to want to include that support as default. Rather than setting it in various defconfigs, simply make CONFIG_MIPS_MT_SMP default y such that systems which select CONFIG_SYS_SUPPORTS_MULTITHREADING get it by default. As well as allowing us to remove the selection of CONFIG_MIPS_MT_SMP from various defconfigs, this also allows the generated generic defconfigs which derive from generic_defconfig to automatically gain support for MT ASE SMP when building for a suitable (pre-MIPSr6) ISA. For malta_kvm_guest_defconfig CONFIG_MIPS_MT_SMP is explicitly disabled since enabling SMP implicitly disables CONFIG_KVM_GUEST, which depends on CONFIG_BROKEN_ON_SMP. Signed-off-by:
-
Paul Burton authored
Using generic_defconfig directly is unlikely to be what a user actually wants to do - it doesn't specify any particular ISA revision & it doesn't enable any board or driver support, resulting in a largely useless kernel. Prevent users from using it directly, printing a helpful message to point them in the right direction if they attempt to. Signed-off-by:
-
Paul Burton authored
The NI 169445 board uses a little endian MIPS32r2 CPU, and therefore including board support in kernels that are unable to run on such a CPU is pointless. Specify requirements in the board config fragment that cause the NI 169445 board support to only be included in generic kernels that target little endian MIPS32r2 CPUs. For example, NI 169445 support will be included when configuring using 32r2el_defconfig but not when using 64r6_defconfig. Signed-off-by:
Nathan Sullivan <nathan.sullivan@ni.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16945/Signed-off-by:
-
Paul Burton authored
The MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for it in 64 bit kernels is wasteful since those kernels will never run on a SEAD-3. Specify a requirement in the SEAD-3 board config fragment that ensures the board support is only included in 32 bit kernels, by checking that CONFIG_32BIT=y. Signed-off-by:
-
Paul Burton authored
Up until now when configuring a generic kernel all board config fragments have been merged by default unless boards are explicitly selected by the user specifying BOARDS=. In many cases this is sub-optimal, since some boards don't make sense to include in some kernels. For example the MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for the SEAD-3 in a 64 bit kernel is wasteful. This patch introduces support for specifying requirements in board config fragments, using comments formatted like so: # require CONFIG_BLA=y For example the SEAD-3 board could specify that it should only be merged for 32 bit kernels using a requirement line like the following: # require CONFIG_32BIT=y A new generic-board-config.sh script is introduced to handle selecting the board config fragments to merge & calling merge_config.sh to merge them. In order to allow requirements to check Kconfig symbols that are implicitly selected, rather than explicitly specified by generic_defconfig or one of the ISA config fragments, an intermediate .config file is saved & used as a reference when checking requirements. Signed-off-by:
-
Paul Burton authored
As a first step towards supporting multi-cluster systems, detect cores & VPs in secondary clusters & record their cluster information in the cpu_data array. The "VP topology" line printed during boot is extended to display multiple clusters. On a single cluster it shows output like the following: VP topology: {4,4} This would indicate a system with 2 cores which each contain 4 VPs. We extend this to cover multiple clusters in a natural way: VP topology: {4,4},{2,2} This would indicate a system with 2 clusters. The first cluster contains 2 cores which each contain 4 VPs. The second cluster contains 2 cores which each contain 2 VPs. Actually booting these cores & VPs is left to further patches once other pieces are in place. Signed-off-by: -
Paul Burton authored
Modify the functions we use to read information about the topology of the system (the number of cores, VPs & IOCUs that it contains) in order to take into account multiple clusters, and provide a new function to determine the number of clusters in the system. Users of these functions are modified only such that they continue to build successfully - having them actually handle multiple clusters is left to further patches. Signed-off-by:
-
Paul Burton authored
With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by:
-
Paul Burton authored
Allow the boot_secondary SMP op to return an error to __cpu_up(), which will in turn return it to its caller. This will allow SMP implementations to return errors quickly in cases they they know have failed, rather than relying upon __cpu_up() eventually timing out waiting for the cpu_running completion. Signed-off-by:
-
Paul Burton authored
With CM >= 3.5 we have the notion of multiple clusters & can access their CM, CPC & GIC registers via the apporpriate redirect/other register blocks. In order to allow for this introduce cluster & block arguments to mips_cm_lock_other() which configures the redirect/other region to point at the appropriate cluster, core, VP & register block. Since we now have 4 arguments to mips_cm_lock_other() & a common use is likely to be to target the cluster, core & VP corresponding to a particular Linux CPU number we also add a new mips_cm_lock_other_cpu() helper function which handles that without the caller needing to manually pull out the cluster, core & VP numbers. Signed-off-by:
-
