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  1. 08 Feb, 2018 2 commits
  3. 06 Feb, 2018 4 commits
  5. 05 Feb, 2018 5 commits
  7. 24 Jan, 2018 3 commits
  9. 23 Jan, 2018 2 commits
  11. 22 Jan, 2018 8 commits
    • James Hogan's avatar
      MIPS: MSA: Update helpers to use new asm macros · 93738d48
      James Hogan authored 
      Update MSA control register access helpers to use the new helpers for
parsing register names and creating custom assembly macro instructions.

This allows the move via $at to be dropped (saving a total of about 20
bytes of kernel code).

Note, this does not alter the equivalent code in .S files, which still
uses the $at trick.
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17776/
      93738d48
    • James Hogan's avatar
      MIPS: XPA: Standardise readx/writex accessors · abbd52fd
      James Hogan authored 
      Now that we are using assembler macros to implement XPA instructions on
toolchains which don't support them, pass Cop0 register names to the
__{readx,writex}_32bit_c0_register macros in $n format rather than
register numbers. Also pass a register select which may be useful in
future (for example for MemoryMapID field of WatchHi registers on
I6500).

This is to make them consistent with the normal Cop0 register access
macros which they were originally based on.
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17777/
      abbd52fd
    • James Hogan's avatar
      MIPS: XPA: Allow use of $0 (zero) to MTHC0 · 3478ba99
      James Hogan authored 
      Tweak __writex_32bit_c0_register() to allow the compiler to use $0 (the
zero register) as an input to the mthc0 instruction.
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17774/
      3478ba99
    • James Hogan's avatar
      MIPS: XPA: Use XPA instructions in assembly · 8e4789d2
      James Hogan authored 
      Utilise XPA instructions MFHC0 & MTHC0 in inline assembly instead of
directly encoding them with the _ASM_INSN* macros, and transparently
implement these instructions as assembler macros if the toolchain
doesn't support them natively, using the recently introduced assembler
macro helpers.

The old direct encodings were restricted to using the register $at, so
this allows the extra register moves to go away (saving a grand total of
24 bytes).
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17775/
      8e4789d2
    • James Hogan's avatar
      MIPS: VZ: Pass GC0 register names in $n format · ed21e007
      James Hogan authored 
      Now that we are using assembler macros to implement VZ instructions on
toolchains which don't support them, pass VZ guest Cop0 register names
to the __{read,write}_{32bit,ulong,64bit}_gc0_register macros in $n
format rather than register numbers. This is to make them consistent
with the normal root Cop0 register access macros which they were
originally based on.
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17773/
      ed21e007
    • James Hogan's avatar
      MIPS: VZ: Update helpers to use new asm macros · 00b4eb40
      James Hogan authored 
      Update VZ guest register & guest TLB access helpers to use the new
assembly macros for parsing register names and creating custom assembly
macro instructions, which has a number of advantages:

 - Better code can be generated on toolchains which don't support VZ,
   more closely matching those which do, since there is no need to
   bounce values via the $at register. Some differences still remain due
   to the inability to safely fill branch delay slots and R6 compact
   branch forbidden slots with explicitly encoded instructions,
   resulting in some extra NOPs added by the assembler.

 - Some code duplication between toolchains which do and don't support
   VZ instructions is removed, since the helpers are only implemented
   once. When the toolchain doesn't implement the instruction an
   assembly macro implements it instead.

 - Instruction encodings are kept together in the source.

On a generic kernel with KVM VZ support enabled this change saves about
2.5KiB of kernel code when TOOLCHAIN_SUPPORTS_VIRT=n, bringing it down
to about 0.5KiB more than when TOOLCHAIN_SUPPORTS_VIRT=y on r6, and just
68 bytes more on r2.
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17772/
      00b4eb40
    • James Hogan's avatar
      MIPS: Add helpers for assembler macro instructions · fc62f53b
      James Hogan authored 
      Implement a parse_r assembler macro in asm/mipsregs.h to parse a
register in $n form, and a few C macros for defining assembler macro
instructions. These can be used to more transparently support older
binutils versions which don't support for example the msa, virt, xpa, or
crc instructions.

In particular they overcome the difficulty of turning a register name in
$n form into an instruction encoding suitable for giving to .word /
.hword, which is particularly problematic when needed from inline
assembly where the compiler is responsible for register allocation.
Traditionally this had required the use of $at and an extra MOV
instruction, but for CRC instructions with multiple GP register operands
that approach becomes more difficult.

Three assembler macro creation helpers are added:

 - _ASM_MACRO_0(OP, ENC)
   This is to define an assembler macro for an instruction which has no
   operands, for example the VZ TLBGR instruction.

 - _ASM_MACRO_2R(OP, R1, R2, ENC)
   This is to define an assembler macro for an instruction which has 2
   register operands, for example the CFCMSA instruction.

 - _ASM_MACRO_3R(OP, R1, R2, R3, ENC)
   This is to define an assembler macro for an instruction which has 3
   register operands, for example the crc32 instructions.

 - _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)
   This is to define an assembler macro for a Cop0 move instruction,
   with 2 register operands and an optional register select operand
   which defaults to 0, for example the VZ MFGC0 instruction.
Suggested-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Marcin Nowakowski <marcin.nowakowski@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17770/
      fc62f53b
    • Miodrag Dinic's avatar
      MIPS: ranchu: Add Ranchu as a new generic-based board · f2d0b0d5
      Miodrag Dinic authored 
      Provide amendments to the MIPS generic platform framework so that
the new generic-based board Ranchu can be chosen to be built.

The Ranchu board is intended to be used by Android emulator. The name
"Ranchu" originates from Android development community. "Goldfish" and
"Ranchu" are terms used for two generations of virtual boards used by
Android emulator. The name "Ranchu" is a newer one among the two, and
this patch deals with Ranchu. However, for historical reasons, some
devices/drivers still contain the name "Goldfish".

MIPS Ranchu machine includes a number of Goldfish devices. The support
for Virtio devices is also included. Ranchu board supports up to 16
Virtio devices which can be attached using Virtio MMIO Bus. This is
summarized in the following picture:

       ABUS
        ||----MIPS CPU
        ||       |                    IRQs
        ||----Goldfish PIC------------(32)--------
        ||                     | | | | | | | | |
        ||----Goldfish TTY------ | | | | | | | |
        ||                       | | | | | | | |
        ||----Goldfish RTC-------- | | | | | | |
        ||                         | | | | | | |
        ||----Goldfish FB----------- | | | | | |
        ||                           | | | | | |
        ||----Goldfish Events--------- | | | | |
        ||                             | | | | |
        ||----Goldfish Audio------------ | | | |
        ||                               | | | |
        ||----Goldfish Battery------------ | | |
        ||                                 | | |
        ||----Android PIPE------------------ | |
        ||                                   | |
        ||----Virtio MMIO Bus                | |
        ||    |    |    |                    | |
        ||    |    |   (virtio-block)--------- |
        ||   (16)  |                           |
        ||    |   (virtio-net)------------------

Device Tree is created on the QEMU side based on the information about
devices IO map and IRQ numbers. Kernel will load this DTB using UHI
boot protocol DTB handover mode.
Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@mips.com>
Signed-off-by: default avatarGoran Ferenc <goran.ferenc@mips.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@mips.com>
Reviewed-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18138/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      f2d0b0d5
  13. 18 Jan, 2018 16 commits
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