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  1. 21 Oct, 2018 5 commits
  3. 19 Oct, 2018 5 commits
    • Vignesh R's avatar
      spi: omap2-mcspi: Add slave mode support · 89e8b9cb
      Vignesh R authored 
      Add support to use McSPI controller as SPI slave. In slave mode, DMA TX
completion does not mean entire data has been shifted out as data might
still be stuck in FIFO waiting for master to clock the bus. Therefore,
add an IRQ handler for slave mode to know when entire data in FIFO has
been shifted out.
Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      89e8b9cb
    • Vignesh R's avatar
      spi: omap2-mcspi: Set FIFO DMA trigger level to word length · b682cffa
      Vignesh R authored 
      McSPI has 32 byte FIFO in Transmit-Receive mode. Current code tries to
configuration FIFO watermark level for DMA trigger to be GCD of transfer
length and max FIFO size which would mean trigger level may be set to 32
for transmit-receive mode if length is aligned. This does not work in
case of SPI slave mode where FIFO always needs to have data ready
whenever master starts the clock. With DMA trigger size of 32 there will
be a small window during slave TX where DMA is still putting data into
FIFO but master would have started clock for next byte, resulting in
shifting out of stale data. Similarly, on Slave RX side there may be RX
FIFO overflow
Fix this by setting FIFO watermark for DMA trigger to word
length. This means DMA is triggered as soon as FIFO has space for word
length bytes and DMA would make sure FIFO is almost always full
therefore improving FIFO occupancy in both master and slave mode.
Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      b682cffa
    • Vignesh R's avatar
      spi: omap2-mcspi: Switch to readl_poll_timeout() · 13d515c7
      Vignesh R authored 
      Use standard readl_poll_timeout() macro for polling on status bits.
Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      13d515c7
    • Ludovic Barre's avatar
      spi: spi-mem: add stm32 qspi controller · c530cd1d
      Ludovic Barre authored 
      The qspi controller is a specialized communication interface
targeting single, dual or quad SPI Flash memories (NOR/NAND).

It can operate in any of the following modes:
-indirect mode: all the operations are performed using the quadspi
 registers
-read memory-mapped mode: the external Flash memory is mapped to the
 microcontroller address space and is seen by the system as if it was
 an internal memory

tested on:
-NOR: mx66l51235l
-NAND: MT29F2G01ABAGD
Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      c530cd1d
    • Ludovic Barre's avatar
      dt-bindings: spi: add stm32 qspi controller · c3e6845e
      Ludovic Barre authored 
      This patch adds the documentation of device tree bindings
for the STM32 QSPI controller. It is a specialized communication
interface targeting single, dual or quad SPI Flash memories (NOR/NAND).
Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      c3e6845e
  5. 17 Oct, 2018 2 commits
  7. 16 Oct, 2018 1 commit
  9. 15 Oct, 2018 2 commits
  11. 14 Oct, 2018 2 commits
  13. 13 Oct, 2018 11 commits
  15. 12 Oct, 2018 12 commits
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