1. 12 Jan, 2018 2 commits
  2. 15 Dec, 2017 1 commit
    • Tony Lindgren's avatar
      dt-bindings: ti-sysc: Update binding for timers and capabilities · 20a2742e
      Tony Lindgren authored
      The ti-sysc binding does not yet describe the capabilities of the
      interconnect target module. So to make the ti-sysc binding usable
      for configuring the interconnect target module, we need to add few
      more properties:
      
      1. To detect between omap2 and omap4 timers, let's add compatibles
         for them for "ti,sysc-omap2-timer" and,sysc-omap4-timer". This
         makes it easier to pick up the already initialized system timers
         later on
      
      2. Let's add "ti,sysc-mask" for a mask of features supported by the
         interconnect target module. This describes what we have available
         in the various SYSCONFIG registers
      
      3. Let's add "ti,sysc-midle" and "ti,sysc-sidle" lists for the master
         and slave idle modes supported by the interconnect target module.
         These describe the values available for MIDLE and SIDLE bits in
         the SYSCONFIG registers
      
      4. Some interconnect target modules need a short delay after reset
         before they can be accessed, let's use "ti,sysc-delay-us" for
         that
      
      5. Let's add "ti,syss-mask" bit to describe the optional SYSSTATUS
         register bits for reset done bits
      
      6. Let's support the two existing custom quirk properties already
         listed in Documentation/devicetree/bindings/arm/omap/omap.txt for
         "ti,no-reset-on-init" and "ti,no-idle-on-init"
      
      7. And finally, let's add a header for the binding for the dts
         files and the driver to use
      
      Cc: Benoît Cousson <bcousson@baylibre.com>
      Cc: Dave Gerlach <d-gerlach@ti.com>
      Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
      Cc: Liam Girdwood <lgirdwood@gmail.com>
      Cc: Mark Brown <broonie@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
      Cc: Sakari Ailus <sakari.ailus@iki.fi>
      Cc: Suman Anna <s-anna@ti.com>
      Cc: Tero Kristo <t-kristo@ti.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      20a2742e
  3. 11 Dec, 2017 24 commits
  4. 04 Dec, 2017 7 commits
  5. 01 Dec, 2017 6 commits