1. 07 May, 2020 1 commit
  2. 04 May, 2020 1 commit
  3. 02 May, 2020 3 commits
  4. 30 Apr, 2020 3 commits
  5. 29 Apr, 2020 9 commits
  6. 28 Apr, 2020 2 commits
  7. 26 Apr, 2020 3 commits
    • Jiaxun Yang's avatar
      MIPS: Kernel: Identify Loongson-2K processors · 0cf2ea11
      Jiaxun Yang authored
      Loongson-2K (Loongson64 Reduced) is a family of SoC shipped with
      gs264e core.
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
      0cf2ea11
    • Tiezhu Yang's avatar
      MIPS: Loongson: Add support for perf tool · e2e13925
      Tiezhu Yang authored
      In order to use perf tool on the Loongson platform, we should enable kernel
      support for various performance events provided by software and hardware,
      so add CONFIG_PERF_EVENTS=y to loongson3_defconfig.
      
      E.g. without this patch:
      
      [loongson@localhost perf]$ ./perf list
      
      List of pre-defined events (to be used in -e):
      
        duration_time                                      [Tool event]
      
        rNNN                                               [Raw hardware event descriptor]
        cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware event descriptor]
         (see 'man perf-list' on how to encode it)
      
        mem:<addr>[/len][:access]                          [Hardware breakpoint]
      
      With this patch:
      
      [loongson@localhost perf]$ ./perf list
      
      List of pre-defined events (to be used in -e):
      
        branch-instructions OR branches                    [Hardware event]
        branch-misses                                      [Hardware event]
        cpu-cycles OR cycles                               [Hardware event]
        instructions                                       [Hardware event]
      
        alignment-faults                                   [Software event]
        bpf-output                                         [Software event]
        context-switches OR cs                             [Software event]
        cpu-clock                                          [Software event]
        cpu-migrations OR migrations                       [Software event]
        dummy                                              [Software event]
        emulation-faults                                   [Software event]
        major-faults                                       [Software event]
        minor-faults                                       [Software event]
        page-faults OR faults                              [Software event]
        task-clock                                         [Software event]
      
        duration_time                                      [Tool event]
      
        L1-dcache-load-misses                              [Hardware cache event]
        L1-dcache-store-misses                             [Hardware cache event]
        L1-icache-load-misses                              [Hardware cache event]
        branch-load-misses                                 [Hardware cache event]
        branch-loads                                       [Hardware cache event]
        dTLB-load-misses                                   [Hardware cache event]
        dTLB-store-misses                                  [Hardware cache event]
        iTLB-load-misses                                   [Hardware cache event]
      
        rNNN                                               [Raw hardware event descriptor]
        cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware event descriptor]
         (see 'man perf-list' on how to encode it)
      
        mem:<addr>[/len][:access]                          [Hardware breakpoint]
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
      e2e13925
    • Huacai Chen's avatar
      MIPS: Rename the "Fill" cache ops to avoid build failure · a44f8309
      Huacai Chen authored
      MIPS define a "Fill" macro as a cache operation in cacheops.h, this
      will cause build failure under some special configurations because in
      seq_file.c there is a "Fill" label. To avoid this failure we rename the
      "Fill" macro to "Fill_I" which has the same coding style as other cache
      operations in cacheops.h (we think renaming the "Fill" macro is more
      reasonable than renaming the "Fill" label).
      
      Callers of "Fill" macro is also updated.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
      a44f8309
  8. 24 Apr, 2020 5 commits
  9. 21 Apr, 2020 4 commits
  10. 20 Apr, 2020 6 commits
  11. 19 Apr, 2020 3 commits