- 21 Sep, 2016 16 commits
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Icenowy Zheng authored
The UART1 at PG (PG6, PG7, PG8, PG9) is, in the Allwinner's reference tablet design of A23/33, used to connect to UART Bluetooth cards. Add the pinmux for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jorik Jonker authored
These peripherals can only be muxed to these pins, so they are associated in the DTSI instead of the board files. This makes it very easy to enable them using overlays or u-boot commands: => fdt set /soc/i2c@01c2ac00 status okay Signed-off-by: Jorik Jonker <jorik@kippendief.biz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jorik Jonker authored
These are the only possible pins for these peripherals according to the datasheet. Signed-off-by: Jorik Jonker <jorik@kippendief.biz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jorik Jonker authored
These H3 boards all expose UART1-3 on their expansion header. Since other functions can be muxed to these pins, they are explicitly disabled. To enable them, one could use DT overlays or U-boot commands: => fdt set /soc/serial@01c28c00 status okay Signed-off-by: Jorik Jonker <jorik@kippendief.biz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jorik Jonker authored
This was done to make UART1-3 on H3 consistent, and less complicated to enable UART1-3 on the breakout header on the several H3 board (notably Orange Pi's). This patch adds a bit of complexity for the existing Banana Pi, which already had the RTS/CTS associated on UART1. The RTS/CTS for UART2-3 could be defined in the same way, but since there is no actual use case for them at the moment, they are left out. Signed-off-by: Jorik Jonker <jorik@kippendief.biz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jorik Jonker authored
These are the pinmux definitions for UART2-3 on H3. These UARTs can only be muxed to these pins, so _a and @0 do not really make sense. I have left out RTS/CTS, since these are rarely used. These can easily be enabled using an additional pinmux set. Signed-off-by: Jorik Jonker <jorik@kippendief.biz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
EHCI1 provides an HSIC interface. This interface is exposed on the board through two pins among the GPIO header. With the PHY now powered up and responding, enabling the interface when nothing is connected results in a lot of error messages: usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71 usb 2-1: new high-speed USB device number 3 using ehci-platform usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71 usb 2-1: new high-speed USB device number 4 using ehci-platform usb 2-1: device not accepting address 4, error -71 usb 2-1: new high-speed USB device number 5 using ehci-platform usb 2-1: device not accepting address 5, error -71 usb usb2-port1: unable to enumerate USB device Disable it by default, but leave the entries in the board DTS. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP806 PMIC is the secondary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP806 PMIC is the secondary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP809's SW (switch) regulator is unused on the Cubieboard 4. Add an empty node for it so that the OS can generate constraints. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP809's SW (switch) regulator is unused on the A80 Optimus. Add an empty node for it so that the OS can generate constraints. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
The ga10h tablet has a gsl3675 touchscreen, add a dt node describing it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Hans de Goede authored
Add a node enabling the gsl3670 touchscreen controller found on sun8i-a23-polaroid-mid2809pxe04 tablets. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Hans de Goede authored
Add a node enabling the gsl1680 touchscreen controller found on sun8i-a23-polaroid-mid2407pxe03 tablets. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Hans de Goede authored
The inet86dz tablet has a gsl1680 touchscreen, add a dt node describing it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Hans de Goede authored
The gt90h tablet has a gsl3675 touchscreen, add a dt node describing it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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- 11 Sep, 2016 2 commits
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Mylène Josserand authored
The GR8-EVB is a small board with an NextThing GR8, an Hynix MLC NAND, an AXP209 PMIC, USB host and OTG, an SPDIF output and a connectors for CSI, I2S and LCD. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Mylène Josserand authored
The GR8 is an SoC made by Nextthing loosely based on the sun5i family. Since it's not clear yet what we can factor out and merge with the A10s and A13 support, let's keep it out of the sun5i.dtsi include tree. We will figure out what can be shared when things settle down. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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- 10 Sep, 2016 14 commits
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Chen-Yu Tsai authored
The usbphy and usb_otg nodes in the A23 and A33 dts files only differ by compatible, and for the usbphy, the size of one of its register regions. Move all the common bits to the A23/A33 common dtsi file. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
The LCD output needs to be muxed. Add the proper pinctrl node. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
Add all the needed blocks to the A33 DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
Now that we have support for the CCU driver in sunxi-ng, convert the A23 and A33 DTs to that driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Chen-Yu Tsai authored
Now that we have a different clock representation, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
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Jean Delvare authored
The sunxi-ng clock driver is useless for other architectures. Signed-off-by: Jean Delvare <jdelvare@suse.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Add support for the clock unit found in the A23. Due to the similarities with the A33, it also shares its clock IDs to allow sharing the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
This commit introduces the clocks found in the Allwinner A33 CCU. Since this SoC is very similar to the A23, and we share a significant share of the DTSI, the clock IDs that are going to be used will also be shared with the A23, hence the name of the various header files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
Add support for the class with a single factor, N, being a multiplier. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
Add a new macro to declare muxes based on a table and a gate. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
Some dividers might have a maximum value that is lower than the width of the register. Add a field to _ccu_div to handle those case properly. If the field is set to 0, the code will assume that the maximum value is the maximum one that can be used with the field register width. Otherwise, we'll use whatever value has been set. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
The internal _ccu_div structure is meant to be embedded into other structures to combine the various dividers and to form the clock classes support. Start to document those structures by using kerneldoc. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Add some macros to ease the declaration of clocks that are using them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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- 06 Sep, 2016 2 commits
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James Pettigrew authored
Guangzhou FriendlyARM Computer Tech Co., Ltd is a Chinese ARM board vendor. Signed-off-by: James Pettigrew <james@innovum.com.au> Reviewed-by: Rask Ingemann Lambertsen <ccc94453@vip.cybercity.dk> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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James Pettigrew authored
The NanoPi NEO is a minimal H3 based SBC. It comes with 256/512M RAM, a micro SD slot, 10/100Mbit ethernet and a single USB-A port. Signed-off-by: James Pettigrew <james@innovum.com.au> Reviewed-by: Rask Ingemann Lambertsen <ccc94453@vip.cybercity.dk> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 05 Sep, 2016 3 commits
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Hans de Goede authored
Most of the sun8i q8 boards have an SDIO wifi controller, on the variants which use an USB wifi controller, this will result in a couple of error msg-s in dmesg when proving the sdio bus and an used mmc controller. The best way to deal with wifi on this boards really is to simply let the kernel auto-detect usb or sdio wifi controllers, so we will just have to live with the few errors in dmesg. This has been tested on a23 based q8 tablets with ESP8089, RTL8703AS and RTL8189FTV wifi controllers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus, with 2G RAM and an external gbit ethernet phy. Note currently the dts is pretty much empty (except for including the pc-plus dts), I've a local patch which enables the emac actually making this dts different from the pc-plus one, but that needs the h3 emac driver to get merged first. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Update the sun8i-h3-orangepi-plus.dts model string to reflect that it is valid for both the Orange Pi Plus and the Orange Pi Plus 2. This is also meant to help users realize that it is not valid for the new Orange Pi Plus 2E, which will get its own dts. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 31 Aug, 2016 1 commit
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Milo Kim authored
Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 27 Aug, 2016 2 commits
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Icenowy Zheng authored
The inet-d978_rev2 is a pcb used in generic A33 based tablets. It features volume buttons, micro-usb otg, headphone connector and a power button. On the board a Realtek RTL8723BS SDIO Wi-Fi module are soldered, and there is also a accompanied board which has a Goodix GT9271 soldered. As this board is desired to create tablets with a Home key dealed by GT9271, a LED is present at the front panel at the position of the Home key. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The R_PIO device node is missing #interrupt-cells, which causes interrupt parsing to fail to match it as a valid interrupt controller. Add #interrupt-cells to it. Also remove the unnecesary #address-cells and #size-cells. Fixes: 1ac56a6d ("ARM: dts: sun9i: Add A80 R_PIO pin controller device node") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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