- 26 Jan, 2008 38 commits
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
There's no point building standby/sleep code for processors which aren't configured. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
PXA3 has a different memory controller from PXA2 platforms. Avoid clashing definitions by moving the PXA2 definitions to pxa2xx-regs.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
The mapping for physical address 0x48000000 is not sufficient to allow access to the dynamic memory controller configuration registers on PXA3. These registers need to be accessed to reconfigure the SDRAM when waking from a low power mode. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Bridge Wu authored
This patch is to add the third mmc controller support _only_ for pxa310. On zylonite, the third controller support one slot. Signed-off-by: Bridge Wu <bridge.wu@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Bridge Wu authored
This patch is to add the second mmc controller support for pxa3xx. It's valid for pxa3[0|1|2]0. On zylonite, the second controller has no slot. Signed-off-by: Bridge Wu <bridge.wu@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Bridge Wu authored
This patchis to add the first mmc controller support for pxa3xx. It's valid for pxa3[0|1|2]0. On zylonite, the first controller supports two slots, this patch only support the first one right now. Signed-off-by: Bridge Wu <bridge.wu@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Considering that generic.c is getting more and more bloated by device information, moving that part out side will be much cleaner. Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Philipp Zabel authored
FFUART and friends are already defined as __REG(x) in pxa-regs.h. Instead of redefining them here, we can just provide the __REG macro. Including asm/arch/hardware.h is not an option because this physical addresses are needed here. This is a fix for the compiler warnings generated by 4663/1. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Bridge Wu authored
This patch is to move pxamci DMA specific code to corresponding platform layer because using DRCMRRXMMC/DRCMRTXMMC in pxamci.c makes the driver code dedicated to platform which is not extensible. It is applicable to all pxa platforms. Signed-off-by: Bridge Wu <bridge.wu@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Bridge Wu authored
pxa3[0|1]0 mmc controller can support 26MHz clock mode, they support SD spec 1.1 and MMC spec 4.0 which specify high speed mode. So host caps will include MMC_CAP_MMC_HIGHSPEED and MMC_CAP_SD_HIGHSPEED for pxa3[0|1]0. This patch is to add 26MHz support for them. pxa host clock will be set to 26MHz mode when the card supported max clock rate is higher than or equal to 26MHz. Signed-off-by: Bridge Wu <bridge.wu@marvell.com> Acked-by: Pierre Ossman <drzeus@drzeus.cx> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
There have been patches hanging around for ages to add support for cpufreq to PXA255 processors. It's about time we applied one. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Initialise the SSP driver at arch_initcall() time, so it's available for other drivers to use it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Only register the "cpld_irq" sysclass for mainstone/lubbock if we're running on one of those platforms. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
1. make pxa2xx_spi.c use ssp_request() and ssp_free() to get the common information of the designated SSP port. 2. remove those IRQ/memory request code, ssp_request() has done that for the driver 3. the SPI platform device is thus made psuedo, no resource (memory/IRQ) has to be defined, all will be retreived by ssp_request() 4. introduce ssp_get_clk_div() to handle controller difference in clock divisor setting 5. use clk_xxx() API for clock enable/disable, and clk_get_rate() to handle the different SSP clock frequency between different processors Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
1. change SSP register definitions from absolute virtual addresses to offsets 2. use __raw_writel()/__raw_readl() for functions of ssp_xxxx() Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
1. define "struct ssp_device" for SSP information, which is requested and released by function ssp_request()/ssp_free() 2. modify the ssp_init() and ssp_exit() to use the interface Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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eric miao authored
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Philipp Zabel authored
Also, use existing register and bit definitions instead of numbers. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Replace wakeup support using the alarm via the SA1100 RTC driver on SA1100 and PXA platforms. This allows RTC alarm wakeup to be enabled via sysfs using the conventional attributes. Acked-by: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
OSCR is supposed to monotonically increment; however restoring it to a time prior to OSMR0 may result in it being wound backwards. Instead, if OSMR0 is within the minimum expiry time, wind OSMR0 forwards. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Apparantly, the generic time subsystem can accurately emulate periodic mode via the one-shot support code, so we don't need our own periodic emulation code anymore. Just ensure that we build support for one shot into the generic time subsystem. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Linux has framebuffer backlight support infrastructure which should be used to expose backlight attributes. Mainstone should use it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Only register the MMC, framebuffer, I2C and FICP devices when the platform supplies the necessary platform data structures for the devices. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6Linus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6: (200 commits) [SCSI] usbstorage: use last_sector_bug flag universally [SCSI] libsas: abstract STP task status into a function [SCSI] ultrastor: clean up inline asm warnings [SCSI] aic7xxx: fix firmware build [SCSI] aacraid: fib context lock for management ioctls [SCSI] ch: remove forward declarations [SCSI] ch: fix device minor number management bug [SCSI] ch: handle class_device_create failure properly [SCSI] NCR5380: fix section mismatch [SCSI] sg: fix /proc/scsi/sg/devices when no SCSI devices [SCSI] IB/iSER: add logical unit reset support [SCSI] don't use __GFP_DMA for sense buffers if not required [SCSI] use dynamically allocated sense buffer [SCSI] scsi.h: add macro for enclosure bit of inquiry data [SCSI] sd: add fix for devices with last sector access problems [SCSI] fix pcmcia compile problem [SCSI] aacraid: add Voodoo Lite class of cards. [SCSI] aacraid: add new driver features flags [SCSI] qla2xxx: Update version number to 8.02.00-k7. [SCSI] qla2xxx: Issue correct MBC_INITIALIZE_FIRMWARE command. ...
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git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: [CRYPTO] hifn795x: Disallow built-in hifn795x when HW_RANDOM is m
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git://git.kernel.org/pub/scm/linux/kernel/git/mfasheh/ocfs2Linus Torvalds authored
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mfasheh/ocfs2: (31 commits) ocfs2: clean up bh null checks ocfs2: document access rules for blocked_lock_list configfs: file.c fix possible recursive locking configfs: dir.c fix possible recursive locking configfs: Remove EXPERIMENTAL ocfs2: bump version number ocfs2/dlm: Clear joining_node on hearbeat node down ocfs2: convert byte order of constant instead of variable ocfs2: Update default cluster timeouts ocfs2: printf fixes ocfs2: Use generic_file_llseek ocfs2: Safer read_inline_data() ocfs2: Silence false lockdep warnings [PATCH 2/2] ocfs2: cluster aware flock() [PATCH 1/2] ocfs2: add flock lock type ocfs2: Local alloc window size changeable via mount option ocfs2: Support commit= mount option ocfs2: Add missing permission checks [PATCH 2/2] ocfs2: Implement group add for online resize [PATCH 1/2] ocfs2: Add group extend for online resize ...
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git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-devLinus Torvalds authored
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (67 commits) fix drivers/ata/sata_fsl.c double-decl [libata] Prefer SCSI_SENSE_BUFFERSIZE to sizeof() pata_legacy: Merge winbond support ata_generic: Cenatek support pata_winbond: error return pata_serverworks: Fix cable types and cosmetics pata_mpc52xx: remove un-needed assignment libata: fix off-by-one in error categorization ahci: factor out AHCI enabling and enable AHCI before reading CAP ata_piix: implement SIDPR SCR access ata_piix: convert to prepare - activate initialization libata: factor out ata_pci_activate_sff_host() from ata_pci_one() [libata] Prefer SCSI_SENSE_BUFFERSIZE to sizeof() pata_legacy: resychronize with upstream changes and resubmit [libata] pata_legacy: typo fix [libata] pata_winbond: update for new ->data_xfer hook pata_pcmcia: convert to new data_xfer prototype libata annotations and fixes libata: use dev_driver_string() instead of "libata" in libata-sff.c ata_piix: kill unused constants and flags ...
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- 25 Jan, 2008 2 commits
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Mark Fasheh authored
If we know a buffer_head is non-null, then brelse() is unnecessary and put_bh() can be used instead. Also, an explicit check for NULL is unnecessary when using brelse(). This patch only covers buffer_head_io.c and resize.c, which have recently added code which exhibits this problem. Signed-off-by: Mark Fasheh <mark.fasheh@oracle.com>
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Mark Fasheh authored
ocfs2_super->blocked_lock_list and ocfs2_super->blocked_lock_count have some usage restrictions which aren't immediately obvious to anyone reading the code. It's a good idea to document this so that we avoid making costly mistakes in the future. Signed-off-by: Mark Fasheh <mark.fasheh@oracle.com>
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