- 11 Oct, 2020 1 commit
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Thomas Gleixner authored
Merge tag 'irqchip-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier: Core changes: - Allow irq retriggering to follow a hierarchy - Allow interrupt hierarchies to be trimmed at allocation time - Allow interrupts to be hidden from /proc/interrupts (IPIs) - Introduce stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER - New per-cpu IPI handling flow Architecture changes: - Move arm/arm64 IPI handling to the core interrupt code, removing the home brewed accounting Driver updates: - New driver for the MStar (and more recently Mediatek) platforms - New driver for the Actions Owl SIRQ controller - New driver for the TI PRUSS infrastructure - Wake-up support for the Qualcomm PDC controller - Primary interrupt controller support for the Designware APB ICTL - Convert the IPI code for GIC, GICv3, hip04, armada-270-xp and bcm2836 to using standard interrupts - Improve GICv3 pseudo-NMI support to deal with both non-secure and secure priorities on arm64 - Convert the GIC/GICv3 drivers to using HW-based irq retrigger - A sprinkling of dev_err_probe() conversion - A set of NVIDIA Tegra fixes for interrupt hierarchy corruption - A reset fix for the Loongson HTVEC driver - A couple of error handling fixes in the TI SCI drivers
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- 10 Oct, 2020 9 commits
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Marc Zyngier authored
Signed-off-by:Marc Zyngier <maz@kernel.org>
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Mark-PK Tsai authored
Add binding for MStar interrupt controller. Signed-off-by:
Mark-PK Tsai <mark-pk.tsai@mediatek.com> Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200902063344.1852-3-mark-pk.tsai@mediatek.com
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Mark-PK Tsai authored
Add MStar interrupt controller support using hierarchy irq domain. Signed-off-by:
Daniel Palmer <daniel@thingy.jp> Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
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Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
The Tegra PMC driver does ungodly things with the interrupt hierarchy, repeatedly corrupting it by pulling hwirq numbers out of thin air, overriding existing IRQ mappings and changing the handling flow of unsuspecting users. All of this is done in the name of preserving the interrupt hierarchy even when these levels do not exist in the HW. Together with the use of proper IRQs for IPIs, this leads to an unbootable system as the rescheduling IPI gets repeatedly repurposed for random drivers... Instead, let's simply mark the level from which the hierarchy does not make sense for the HW, and let the core code trim the usused levels from the hierarchy. Signed-off-by: -
Marc Zyngier authored
Make the PMC driver resistent to variable depth interrupt hierarchy, which we are about to introduce. Signed-off-by: -
Marc Zyngier authored
Make the tegra186 GPIO driver resistent to variable depth interrupt hierarchy, which we are about to introduce. No functionnal change yet. Signed-off-by: -
Marc Zyngier authored
It appears that some HW is ugly enough that not all the interrupts connected to a particular interrupt controller end up with the same hierarchy depth (some of them are terminated early). This leaves the irqchip hacker with only two choices, both equally bad: - create discrete domain chains, one for each "hierarchy depth", which is very hard to maintain - create fake hierarchy levels for the shallow paths, leading to all kind of problems (what are the safe hwirq values for these fake levels?) Implement the ability to cut short a single interrupt hierarchy from a level marked as being disconnected by using the new irq_domain_disconnect_hierarchy() helper. The irqdomain allocation code will then perform the trimming Signed-off-by:
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- 06 Oct, 2020 7 commits
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Marc Zyngier authored
Signed-off-by: -
Maulik Shah authored
Kexec can directly boot into a new kernel without going to complete reboot. This can leave the previous kernel's configuration for PDC interrupts as is. Clear previous kernel's configuration during init by setting interrupts in enable bank to zero. The IRQs specified in qcom,pdc-ranges property are the only ones that can be used by the new kernel so clear only those IRQs. The remaining ones may be in use by a different kernel and should not be set by new kernel. Suggested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Maulik Shah <mkshah@codeaurora.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-7-git-send-email-mkshah@codeaurora.org
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Maulik Shah authored
Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the wakeirqs during suspend entry. Signed-off-by:
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Maulik Shah authored
Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the wakeirqs during suspend entry. Signed-off-by:
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Maulik Shah authored
An interrupt that is disabled/masked but set for wakeup may still need to be able to wake up the system from sleep states like "suspend to RAM". To that effect, introduce the IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag. If the irqchip have this flag set, the irq PM code will enable/unmask the irqs that are marked for wakeup, but that are in a disabled state. On resume, such irqs will be restored back to their disabled state. Suggested-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
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Maulik Shah authored
msmgpio irqchip was not using return value of irq_set_irq_wake() callback since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor it implemented .irq_set_wake callback. This lead to irq_set_irq_wake() return error -ENXIO. However from 'commit 4110b5cb ("irqchip/gic-v3: Allow interrupt to be configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE flag. Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent() instead of always returning success. Fixes: e35a6ae0 ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by:
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Maulik Shah authored
Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked during suspend or during setting irq type since genirq checks irqchip flag of msmgpio irqchip which forwards these calls to its parent PDC irqchip. Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during suspend and mask before setting irq type. Masking before changing type make sures any spurious interrupt is not detected during this operation. Fixes: e35a6ae0 ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by:
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- 28 Sep, 2020 2 commits
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Marc Zyngier authored
Merge branch 'irq/ipi-as-irq', remote-tracking branches 'origin/irq/dw' and 'origin/irq/owl' into irq/irqchip-next Signed-off-by: -
Marc Zyngier authored
As SMP-on-UP is a valid configuration on 32bit ARM, do not assume that IPIs are populated in show_ipi_list(). Reported-by:
Guillaume Tucker <guillaume.tucker@collabora.com> Reported-by:
kernelci.org bot <bot@kernelci.org> Tested-by:
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- 25 Sep, 2020 7 commits
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Cristian Ciocaltea authored
Add entries for Actions Semi Owl SIRQ controller binding and driver. Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Signed-off-by:
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Cristian Ciocaltea authored
This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700 and S900) and provides support for handling up to 3 external interrupt lines. Each line can be independently configured as interrupt and triggers on either of the edges or either of the levels. Additionally, each line can also be masked individually. Co-developed-by:
Parthiban Nallathambi <pn@denx.de> Co-developed-by:
Saravanan Sekar <sravanhome@gmail.com> Signed-off-by:
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Cristian Ciocaltea authored
Actions Semi Owl SoCs SIRQ interrupt controller is found in S500, S700 and S900 SoCs and provides support for handling up to 3 external interrupt lines. Signed-off-by:
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Zhen Lei authored
Add the required updates to describe the use of dw-apb-ictl as a primary interrupt controller. Signed-off-by:
Zhen Lei <thunder.leizhen@huawei.com> [maz: commit message] Signed-off-by:
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Zhen Lei authored
Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by:
Haoyu Lv <lvhaoyu@huawei.com> Link: https://lore.kernel.org/r/20200924071754.4509-4-thunder.leizhen@huawei.com
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Zhen Lei authored
Add the required abstractions that will help introducing hierarchical domain support to the dw-apb-ictl driver. No functional change. Signed-off-by:
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Zhen Lei authored
In order to avoid compilation errors when a driver references set_handle_irq(), but that the architecture doesn't select GENERIC_IRQ_MULTI_HANDLER, add a stub function that will just WARN_ON_ONCE() if ever used. Signed-off-by:
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- 18 Sep, 2020 2 commits
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Marc Zyngier authored
ipi_teardown() is only used when CONFIG_HOTPLUG_CPU is enabled. Move the function to a location guarded by this config option. Signed-off-by: -
YueHaibing authored
If CONFIG_HOTPLUG_CPU is n, gcc warns: arch/arm64/kernel/smp.c:967:13: warning: ‘ipi_teardown’ defined but not used [-Wunused-function] static void ipi_teardown(int cpu) ^~~~~~~~~~~~ Use #ifdef guard this. Signed-off-by:YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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- 17 Sep, 2020 12 commits
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Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
Signed-off-by: -
Marc Zyngier authored
Introduce a static key identifying Samsung's unique creation, allowing to replace the indirect call to compute the base addresses with a simple test on the static key. Faster, cheaper, negative diffstat. Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
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Marc Zyngier authored
Although it doesn't seem possible to disable individual mailbox interrupts, we still need to provide some callbacks. Fixes: 09eb672ce4fb ("irqchip/bcm2836: Configure mailbox interrupts as standard interrupts") Reported-by: -
Marc Zyngier authored
Let's switch the arm code to the core accounting, which already does everything we need. Reviewed-by:
Valentin Schneider <valentin.schneider@arm.com> Signed-off-by:
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Marc Zyngier authored
The old IPI registration interface is now unused on arm, so let's get rid of it. Reviewed-by:
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Marc Zyngier authored
Let's switch the arm64 code to the core accounting, which already does everything we need. Reviewed-by:
Catalin Marinas <catalin.marinas@arm.com> Signed-off-by:
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Marc Zyngier authored
The old IPI registration interface is now unused on arm64, so let's get rid of it. Reviewed-by:
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Marc Zyngier authored
To introduce IPIs as standard interrupts to the Armada 370-XP driver, let's allocate a completely separate irqdomain and irqchip combo that lives parallel to the "standard" one. This effectively should be modelled as a chained interrupt controller, but the code is in such a state that it is pretty hard to shoehorn, as it would require the rewrite of the MSI layer as well. Signed-off-by:
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