1. 16 Apr, 2015 9 commits
    • Daniel Vetter's avatar
      drm/i915: Drop unecessary fb arguments from function signatures · 8805aa71
      Daniel Vetter authored
      This is a separate patch to simplify conflict handling with other
      ongoing atomic work.
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
      Reviewed-by: default avatarAnder Conselvan de Oliveira <conselvan2@gmail.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      8805aa71
    • Daniel Vetter's avatar
      drm/i915: Select starting pipe bpp irrespective or the primary plane · d328c9d7
      Daniel Vetter authored
      Since universal planes the primary plane might not be around, and it's
      kinda silly to restrict the pipe bpp to the primary plane if we might
      end up displaying a 10bpc video overlay. And with atomic we might very
      well enable a pipe without a primary plane. So just use the platform
      max as a starting point and then restrict appropriately.
      
      Of course this is all still a bit moot as long as we artificially
      compress everything to max 8bpc because we don't use the hi-bpc gamma
      tables.
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
      Reviewed-by: default avatarAnder Conselvan de Oliveira <conselvan2@gmail.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d328c9d7
    • Tvrtko Ursulin's avatar
      drm/i915: Fix view type in warning message · 5678ad73
      Tvrtko Ursulin authored
      One month passed between posting a patch and it getting merged, and
      unfortunately even though it still applies, it needs fixing to account
      for changes in function parameters since:
      
         commit d385612e15b8b6eb3db328d83f1872ef8a381788
         Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
         Date:   Tue Mar 17 14:45:29 2015 +0000
      
             drm/i915: Log view type when printing warnings
      Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      [danvet: Squash in fixup from Tvrtko to fix the rebase conflict.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      5678ad73
    • Suketu Shah's avatar
      drm/i915/bxt: Add DC9 Trigger sequence · 31335cec
      Suketu Shah authored
      Add triggers for DC9 as per details provided in bxt_enable_dc9
      and bxt_disable_dc9 implementations.
      
      v1:
      - Add SKL check in gen9_disable_dc5 as it is possible for DC5
        to remain disabled only for SKL.
      - Add additional checks for whether DC5 is already disabled during
        DC5-disabling only for BXT.
      
      v2:
      - rebase to latest.
      - Load CSR during DC9 disabling in the beginning before DC9 is
        disabled.
      - Make gen9_disable_dc5 function non-static as it's being called by
        functions in i915_drv.c.
      - Enable DC9-related functionality using a macro.
      
      v3: (imre)
      - remove BXT_ENABLE_DC9, we want DC9 always, and it's only valid on BXT
      - remove DC5 disabling and CSR FW loaded check, these are nop atm
      - squash in Vandana's "Do ddi_phy_init always" patch
      
      v4:
      - add TODO to re-enable DC5 during resume if CSR FW is available (sagar)
      Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
      Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v2)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarSagar Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      31335cec
    • A.Sunil Kamath's avatar
      drm/i915/bxt: Implement enable/disable for Display C9 state · 664326f8
      A.Sunil Kamath authored
      v2: Modified as per review comments from Imre
      - Mention enabling instead of allowing in the debug trace and
        remove unnecessary comments.
      
      v3:
      - Rebase to latest.
      - Move DC9-related functions from intel_display.c to intel_runtime_pm.c.
      
      v4: (imre)
      - remove DC5 disabling, it's a nop at this point
      - squashed in Suketu's "Assert the requirements to enter or exit DC9"
        patch
      - remove check for RUNTIME_PM from assert_can_enable_dc9, it's not a
        dependency
      
      Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v3)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarSagar Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      664326f8
    • Imre Deak's avatar
      drm/i915/bxt: add description about the BXT PHYs · eee21566
      Imre Deak authored
      Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
      
      v2:
      - add more detail about the mapping between ports and transcoders (ville)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      eee21566
    • Vandana Kannan's avatar
      drm/i915/bxt: add display initialize/uninitialize sequence (PHY) · 5c6706e5
      Vandana Kannan authored
      Add PHY specific display initialization sequence as per BSpec.
      
      Note that the PHY initialization/uninitialization are done
      at their current place only for simplicity, in a future patch - when more
      of the runtime PM features will be enabled - these will be moved to
      power well#1 and modeset encoder enabling/disabling hooks respectively.
      
      The call to uninitialize the PHY during system/runtime suspend will be
      added later in this patchset.
      
      v1: Added function definitions in header files
      v2: Imre's review comments addressed
      - Moved CDCLK related definitions to i915_reg.h
      - Removed defintions for CDCLK frequency
      - Split uninit_cdclk() by adding a phy_uninit function
      - Calculate freq and decimal based on input frequency
      - Program SSA precharge based on input frequency
      - Use wait_for 1ms instead 200us udelay for DE PLL locking
      - Removed initial value for divider, freq, decimal, ratio.
      - Replaced polling loops with wait_for
      - Parameterized latency optim setting
      - Fix the parts where DE PLL has to be disabled.
      - Call CDCLK selection from mode set
      
      v3: (imre)
      - add note about the plan to move the cdclk/phy init to a better place
      - take rps.hw_lock around pcode access
      - fix DDI PHY timeout value
      - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
        "DDI PHY programming register defn", "Do ddi_phy_init always",
      - move PHY register macros next to the corresponding CHV/VLV macros
      - move DE PLL register macros here from another patch since they are
        used here first
      - add BXT_ prefix to CDCLK flags
      - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
      - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
      - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
        when powering on DDI ports
      - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
      - add missing masking when programming CDCLK_FREQ_DECIMAL
      - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
        to OCL2_LDOFUSE_PWR_DIS to reduce confusion
      - add note about mismatch with bspec in the PORT_REF_DW6 fields
      - factor out PHY init code to a new function, so we can call it for
        PHY1 and PHY0, instead of open-coding the same
      
      v4: (ville)
      - split the CDCLK/PHY parts into two patches, update commit message
        accordingly
      - use the existing dpio_phy enum instead of adding a new one for the
        same purpose
      - flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
        better match CHV
      - s/BXT_PHY/_BXT_PHY/
      - use _PIPE for _BXT_PHY instead of open-coding it
      - drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
      - define GT_DISPLAY_POWER_ON in a more standard way
      - make a note that the CHV ConfigDB also disagrees about GRC_CODE field
        definitions
      - fix lane optimization refactoring fumble from v3
      - add per PHY uninit functions to match the init counterparts
      
      Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      5c6706e5
    • Vandana Kannan's avatar
      drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK) · f8437dd1
      Vandana Kannan authored
      Add CDCLK specific display clock initialization sequence as per BSpec.
      
      Note that the CDCLK initialization/uninitialization are done at their
      current place only for simplicity, in a future patch - when more of the
      runtime PM features will be enabled - these will be moved to power
      well#1 and modeset encoder enabling/disabling hooks respectively. This
      also means that atm dynamic power gating power well #1 is effectively
      disabled.
      
      The call to uninitialize CDCLK during system/runtime suspend will be
      added later in this patchset.
      
      v1: Added function definitions in header files
      v2: Imre's review comments addressed
      - Moved CDCLK related definitions to i915_reg.h
      - Removed defintions for CDCLK frequency
      - Split uninit_cdclk() by adding a phy_uninit function
      - Calculate freq and decimal based on input frequency
      - Program SSA precharge based on input frequency
      - Use wait_for 1ms instead 200us udelay for DE PLL locking
      - Removed initial value for divider, freq, decimal, ratio.
      - Replaced polling loops with wait_for
      - Parameterized latency optim setting
      - Fix the parts where DE PLL has to be disabled.
      - Call CDCLK selection from mode set
      
      v3: (imre)
      - add note about the plan to move the cdclk/phy init to a better place
      - take rps.hw_lock around pcode access
      - move DE PLL register macros here from another patch since they are
        used here first
      - add BXT_ prefix to CDCLK flags
      - add missing masking when programming CDCLK_FREQ_DECIMAL
      
      v4: (ville)
      - split the CDCLK/PHY parts into two patches, update commit message
        accordingly
      - s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/
      - simplify BXT_DE_PLL_RATIO macros
      - fix BXT_DE_PLL_RATIO_MASK
      - s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/
      - move cdclk init/uninit/set code from intel_ddi.c to intel_display.c
      - remove redundant code comments for broxton_set_cdclk_freq()
      - sanitize fixed point<->integer frequency value conversion
      - use DRM_ERROR instead of WARN
      - do RMW when programming BXT_DE_PLL_CTL for safety
      - add note about PLL lock timeout being exactly 200us
      - make PCU error messages more descriptive
      - instead of using 0 freq to mean PLL off/bypass freq use 19200
        for clarity, as the latter one is the actual rate
      - simplify pcode programming, removing duplicated
        sandybridge_pcode_write() call
      - sanitize code flow, remove unnecessary scratch vars in
        broxton_set_cdclk() (imre)
      - Remove bound check for maxmimum freq to match current code.
        This check will be added later at a more proper platform
        independent place once atomic support lands.
      - add note to remove freq guard band which isn't needed on BXT
      - add note to reduce freq to minimum if no pipe is enabled
      - combine broxton_modeset_global_pipes() with
        valleyview_modeset_global_pipes()
      
      Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      f8437dd1
    • Vandana Kannan's avatar
      drm/i915: Rename vlv_cdclk_freq to cdclk_freq · 164dfd28
      Vandana Kannan authored
      Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
      platforms as required. Needed by the next patch.
      Signed-off-by: default avatarVandana Kannan <vandana.kannan@intel.com>
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      164dfd28
  2. 14 Apr, 2015 20 commits
  3. 13 Apr, 2015 11 commits