- 13 May, 2016 40 commits
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Zubair Lutfullah Kakakhel authored
Add basic CN7XXX interface detection. This allows the kernel to boot with ethernet working as it initializes the ethernet ports with SGMII instead of defaulting to RGMII routines. Tested on the utm8 from Rhino Labs with a CN7130. Signed-off-by:
Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Acked-by:
David Daney <david.daney@cavium.com> Cc: janne.huttunen@nokia.com Cc: aaro.koskinen@nokia.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12376/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Avoids function calls to an empty function. Signed-off-by: -
Paul Burton authored
MIPS32 code uses rel-style relocs, and MIPS32r6 modules may include R_MIPS_PC16, R_MIPS_PC21 & R_MIPS_PC26 relocations. We thus need to support these relocations in order to load MIPS32r6 kernel modules. This patch adds such support, which is similar to the rela-style support in module-rela.c but making use of the implicit addend from the instruction encoding. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12435/Signed-off-by:
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Paul Burton authored
MIPS64 code uses rela-style relocs, and MIPS64r6 modules may include the new R_MIPS_PC21 & R_MIPS_PC26 relocations. We thus need to support these relocations in order to load MIPS64r6 kernel modules. They are similar to the existing R_MIPS_PC16 relocation but applying to a wider field. Implement support for them by genericising the existing R_MIPS_PC16 implementation such that it can be used for different field widths, and calling it for all 3 reloc types. Signed-off-by:
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Steven J. Hill authored
The module relocation handling code has inconsistent use of printk() and pr_*() functions. Convert printk() calls to use pr_err() and pr_warn(). [paul.burton@imgtec.com: Do the same thing in module.c] Signed-off-by:
Steven J. Hill <sjhill@realitydiluted.com> Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Paul Burton authored
Support probing the M6250 CPU now that cases for handling it have been added where required in the core MIPS kernel code. Signed-off-by:
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Paul Burton authored
Add casses supporting the M6250 CPU to various switch statements in the core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by:
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Paul Burton authored
Define the processor ID for the M6250 CPU and add a value to the enum cpu_type_enum for the core. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
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Paul Burton authored
Support probing the P6600 core now that cases for handling it have been added throughout the core MIPS kernel code. Signed-off-by:
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Paul Burton authored
Add cases supporting the P6600 CPU to various switch statements in core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by:
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Paul Burton authored
Define the processor ID for the P6600 core and add a value to the enum cpu_type_enum for the core. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
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Ralf Baechle authored
Signed-off-by: -
Paul Burton authored
There are CPUs/bitfiles available for use with SEAD3 boards which implement release 6 of the MIPS architecture. Allow building the kernel for such a system. Signed-off-by:
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Paul Burton authored
When CONFIG_MIPS_CPS_NS16550 is enabled, some register state is dumped to the UART when an exception is taken via the BEV on secondary cores. EJTAG exceptions are architecturally expected to be handled by the BEV even when Status.BEV is 0. This effectively means that if userland executes an sdbbp instruction on a secondary core then the kernel dumps register state to the UART even though the exception is perfectly normal & expected. Prevent this by simply not dumping information to the UART for EJTAG exceptions. Fixes: 609cf6f2 ("MIPS: CPS: Early debug using an ns16550-compatible UART") Signed-off-by:
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Paul Burton authored
When debugging a new system or core it can be useful to disable the use of multithreading. Introduce a "nothreads" kernel command line parameter that can be set in order to do so. Signed-off-by:
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Paul Burton authored
Introduce support for bringing up Virtual Processors in MIPSr6 systems as CPUs, much like their VPE parallel from the now-deprecated MT ASE. The existing mips_cps_boot_vpes function fits the MIPSr6 architecture pretty well - it can now simply write the mask of running VPs to the VC_RUN register, rather than looping through each & starting or stopping as appropriate as is done for VPEs from the MT ASE. Thus the VP support is in general an extension & simplification of the existing MT ASE VPE (aka SMVP) support. Signed-off-by:
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Paul Burton authored
In preparation for supporting MIPSr6 multithreading (ie. VPs) which will begin execution from the core reset vector, skip core level setup if the core is already coherent. This is never the case when a core is first started, since boot_core explicitly clears the cores GCR_Cx_COH_EN register, and always the case when secondary VPs start since the first VP to start will have enabled coherence after initialising the core & its caches. One notable side effect of this patch is that eva_init gets called slightly earlier, prior to mips_cps_core_init rather than after it. Signed-off-by:
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Paul Burton authored
The mips_cps_boot_vpes function previously included code to retrieve pointers to the core & VPE boot configuration structs. These structures were used both by mips_cps_boot_vpes and by its mips_cps_core_entry callsite. In preparation for skipping the call to mips_cps_boot_vpes on some invocations of mips_cps_core_entry, pull the calculation of those pointers out into a separate function such that it can continue to be shared. Signed-off-by:
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Paul Burton authored
In preparation for further modifications to mips_cps_core_entry, pull the L1 cache initialisation out into a separate function. This both makes the code in mips_cps_core_entry read more clearly, particularly when modifying it, and shortens it which will become important as code is added that needs to continue to fit within the reset vector. Signed-off-by:
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Paul Burton authored
When bringing up a CPU, ensure that its local ID as provided by the GIC matches up with our calculation of it. This is vital, since if the condition doesn't hold then we won't have configured interrupts correctly for the VP. Signed-off-by:
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Paul Burton authored
Provide a gic_read_local_vp_id() function to read the VCNUM field of the GICs local VP_IDENT register. This will be used by a further patch to check that the value reported by the GIC matches up with the kernels calculation. Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hogan <james.hogan@imgtec.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12334/Signed-off-by:
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Paul Burton authored
The Linux CPU number doesn't necessarily match up with the ID used for a VP by hardware. Convert the CPU number to the HW ID using mips_cm_vp_id when writing to the VP(E)_OTHER_ADDR register in order to ensure that we correctly access registers for the VPs of secondary cores. This most notably affects systems using CM3, such as those based around I6400. Signed-off-by:
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Paul Burton authored
Fix mips_cm_max_vp_width for UP kernels where it previously referenced smp_num_siblings, which is not declared for UP kernels. This led to build errors such as the following: drivers/built-in.o: In function `$L446': irq-mips-gic.c:(.text+0x1994): undefined reference to `smp_num_siblings' drivers/built-in.o:irq-mips-gic.c:(.text+0x199c): more undefined references to `smp_num_siblings' follow On UP kernels simply return 1, leaving the reference to smp_num_siblings in place only for SMP kernels. Signed-off-by:
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Paul Burton authored
Generate accessor functions for the GCR_BEV_BASE register introduced by CM3, for use by a later patch. Signed-off-by:
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Markos Chandras authored
Add the new CM3 registers for controlling bringing up and powering down VPs on MIPSR6 cores. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:
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Markos Chandras authored
This is similar to commit 934c7923 ("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions"). The CACHE instruction has been redefined for MIPSr6 and it reduced its offset field to 8 bits. This leads to micro-assembler field overflow warnings when booting SMP MIPSr6 cores like the following one: Call Trace: [<ffffffff8010af88>] show_stack+0x68/0x88 [<ffffffff8056ddf0>] dump_stack+0x68/0x88 [<ffffffff801305bc>] warn_slowpath_common+0x8c/0xc8 [<ffffffff80130630>] warn_slowpath_fmt+0x38/0x48 [<ffffffff80125814>] build_insn+0x514/0x5c0 [<ffffffff806ee134>] cps_gen_cache_routine.isra.3+0xe0/0x1b8 [<ffffffff806ee570>] cps_pm_init+0x364/0x9ec [<ffffffff80100538>] do_one_initcall+0x90/0x1a8 [<ffffffff806e8c14>] kernel_init_freeable+0x160/0x21c [<ffffffff8056b6a0>] kernel_init+0x10/0xf8 [<ffffffff801059f8>] ret_from_kernel_thread+0x14/0x1c We fix this by incrementing the base register on every loop. Signed-off-by:
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Markos Chandras authored
We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by:
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Paul Burton authored
MIPSr6 introduces support for "Virtual Processors", which are conceptually similar to VPEs from the now-deprecated MT ASE. Detect whether the system supports VPs using the VP bit in Config5, adding cpu_has_vp for use by later patches. Signed-off-by:
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Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO key and LED. Links: * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=50 * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=63Signed-off-by:
Antony Pavlov <antonynpavlov@gmail.com> Cc: Daan Pape <daan@dptechnics.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12886/Signed-off-by:
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Antony Pavlov authored
Please see https://www.dptechnics.com/contact for details. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Daan Pape <daan@dptechnics.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12885/Signed-off-by:
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Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO key and LED. Please see https://onion.io/omega for details. Signed-off-by:
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Antony Pavlov authored
Please see https://onion.io/contact for details. Signed-off-by:
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Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO keys and LEDs. Links: * http://www.dragino.com/products/mother-board/item/71-ms14-p.html * https://wiki.openwrt.org/toh/dragino/ms14Signed-off-by: -
Antony Pavlov authored
Please see http://www.dragino.com/about/about.html for details. Signed-off-by:
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Antony Pavlov authored
The following features are supported: * UART; * SPI-flash; * USB host; * GPIO keys and LEDs. Links: * http://www.tp-link.com/en/products/details/?model=TL-MR3020 * http://wiki.openwrt.org/toh/tp-link/tl-mr3020 * https://wikidevi.com/wiki/TP-LINK_TL-MR3020Signed-off-by:
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Antony Pavlov authored
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Antony Pavlov authored
This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet). The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC), typically used in very cheap Access Points and Routers. Signed-off-by:
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Antony Pavlov authored
For OF boards we have to skip platform initialization code so we can prove that OF code do all necessary initialization. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Reviewed-by:
Marek Vasut <marex@denx.de> Cc: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12877/ Patchwork: https://patchwork.linux-mips.org/patch/12920/Signed-off-by:
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Antony Pavlov authored
Current ath79 clock.c code does not read reference clock and pll setup from devicetree. E.g. you can set any clock rate value in board DTS but it will have no effect on the real clk calculation. This patch fixes some AR9132 devicetree clock support defects: * clk initialization function ath79_clocks_init_dt_ng() is introduced; it actually gets pll block base register address and reference clock from devicetree; * pll register parsing code is moved to the separate ar724x_clk_init() function; this function can be called from platform code or from devicetree code. Also mips_hpt_frequency value is set from dt, so the appropriate clock parameter is added to the cpu@0 devicetree node. The same approach can be used for adding AR9331 devicetree support. Signed-off-by: -
Antony Pavlov authored
The include/dt-bindings/clock/ath79-clk.h header file is introduced so we can use symbolic identifiers for SoC clocks. Signed-off-by:
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