- 28 Apr, 2020 2 commits
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Tiezhu Yang authored
Read the address of host bridge configuration space to get the vendor ID and device ID of host bridge, and then we can distinguish various types of host bridge such as LS7A or RS780E. Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Jason Yan authored
Fix the following coccicheck warning: arch/mips/oprofile/common.c:113:2-3: Unneeded semicolon Signed-off-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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- 26 Apr, 2020 3 commits
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Jiaxun Yang authored
Loongson-2K (Loongson64 Reduced) is a family of SoC shipped with gs264e core. Signed-off-by:
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Tiezhu Yang authored
In order to use perf tool on the Loongson platform, we should enable kernel support for various performance events provided by software and hardware, so add CONFIG_PERF_EVENTS=y to loongson3_defconfig. E.g. without this patch: [loongson@localhost perf]$ ./perf list List of pre-defined events (to be used in -e): duration_time [Tool event] rNNN [Raw hardware event descriptor] cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descriptor] (see 'man perf-list' on how to encode it) mem:<addr>[/len][:access] [Hardware breakpoint] With this patch: [loongson@localhost perf]$ ./perf list List of pre-defined events (to be used in -e): branch-instructions OR branches [Hardware event] branch-misses [Hardware event] cpu-cycles OR cycles [Hardware event] instructions [Hardware event] alignment-faults [Software event] bpf-output [Software event] context-switches OR cs [Software event] cpu-clock [Software event] cpu-migrations OR migrations [Software event] dummy [Software event] emulation-faults [Software event] major-faults [Software event] minor-faults [Software event] page-faults OR faults [Software event] task-clock [Software event] duration_time [Tool event] L1-dcache-load-misses [Hardware cache event] L1-dcache-store-misses [Hardware cache event] L1-icache-load-misses [Hardware cache event] branch-load-misses [Hardware cache event] branch-loads [Hardware cache event] dTLB-load-misses [Hardware cache event] dTLB-store-misses [Hardware cache event] iTLB-load-misses [Hardware cache event] rNNN [Raw hardware event descriptor] cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descriptor] (see 'man perf-list' on how to encode it) mem:<addr>[/len][:access] [Hardware breakpoint] Signed-off-by:
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Huacai Chen authored
MIPS define a "Fill" macro as a cache operation in cacheops.h, this will cause build failure under some special configurations because in seq_file.c there is a "Fill" label. To avoid this failure we rename the "Fill" macro to "Fill_I" which has the same coding style as other cache operations in cacheops.h (we think renaming the "Fill" macro is more reasonable than renaming the "Fill" label). Callers of "Fill" macro is also updated. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
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- 24 Apr, 2020 5 commits
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Jiaxun Yang authored
XContext might be dirty at boot time. We need to clear it to ensure early stackframe is safe. Signed-off-by:
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Liangliang Huang authored
Use mp_ops->send_ipi_single() instead of mp_ops->send_ipi_mask() in arch_send_call_function_single_ipi(). send_ipi_single() can send IPI signal to a special cpu more efficiently. Signed-off-by:
Liangliang Huang <huangll@lemote.com> Reviewed-by:
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Huacai Chen authored
1, Add unaligned gslq, gssq, gslqc1, gssqc1 emulation; 2, Add unaligned gsl{h, w, d}x, gss{h, w, d}x emulation; 3, Add unaligned gslwxc1, gsswxc1, gsldxc1, gssdxc1 emulation. Signed-off-by:Pei Huang <huangpei@loongson.cn> Reviewed-by:
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Huacai Chen authored
Move unaligned load/store helpers from unaligned.c to inst.h, then other parts of the kernel can use these helpers. Use __ASSEMBLY__ to guard the definition of "LONG" in asm.h to avoid build error on IPxx platforms. Signed-off-by:
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Huacai Chen authored
mm_isBranchInstr() is declared both in branch.h and in fpu_emulator.h but the two declarations are conflict. If both of them are included by a same file, they will cause a build error: ./arch/mips/include/asm/branch.h:33:19: error: static declaration of 'mm_isBranchInstr' follows non-static declaration static inline int mm_isBranchInstr(struct pt_regs *regs, ^ ./arch/mips/include/asm/fpu_emulator.h:177:5: note: previous declaration of 'mm_isBranchInstr' was here int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, Fix this error by removing both isBranchInstr() and mm_isBranchInstr() in fpu_emulator.h, and declaring both of them in branch.h. Signed-off-by:
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- 21 Apr, 2020 4 commits
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Christoph Hellwig authored
Looks like I misread the Kconfig magic and this driver can be compiled into 32-bit kernels. Add back the hack to extent the range of the resource_size_t, and include the header with the txx9-specific ioremap magic for that. Fixes: acfaaf52 ("ASoC: txx9: don't work around too small resource_size_t") Signed-off-by:
Christoph Hellwig <hch@lst.de> Acked-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
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Tiezhu Yang authored
In the current code, if CONFIG_SWIOTLB is set, when failed to get IO TLB memory from the low pages by plat_swiotlb_setup(), it may lead to the boot process failed with kernel panic. (1) On the Loongson and SiByte platform arch/mips/loongson64/dma.c arch/mips/sibyte/common/dma.c void __init plat_swiotlb_setup(void) { swiotlb_init(1); } kernel/dma/swiotlb.c void __init swiotlb_init(int verbose) { ... vstart = memblock_alloc_low(PAGE_ALIGN(bytes), PAGE_SIZE); if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) return; ... pr_warn("Cannot allocate buffer"); no_iotlb_memory = true; } phys_addr_t swiotlb_tbl_map_single() { ... if (no_iotlb_memory) panic("Can not allocate SWIOTLB buffer earlier ..."); ... } (2) On the Cavium OCTEON platform arch/mips/cavium-octeon/dma-octeon.c void __init plat_swiotlb_setup(void) { ... octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE); if (!octeon_swiotlb) panic("%s: Failed to allocate %zu bytes align=%lx\n", __func__, swiotlbsize, PAGE_SIZE); ... } Because IO_TLB_DEFAULT_SIZE is 64M, if the rest size of low memory is less than 64M when call plat_swiotlb_setup(), we can easily reproduce the panic case. In order to reduce the possibility of kernel panic when failed to get IO TLB memory under CONFIG_SWIOTLB, it is better to allocate low memory as small as possible before plat_swiotlb_setup(), so make sparse_init() using top-down allocation. Reported-by:Juxin Gao <gaojuxin@loongson.cn> Co-developed-by:
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Tiezhu Yang authored
In the current code, plat_mem_setup() is called by arch_mem_init() instead of setup_arch() and has been declared in asm/bootinfo.h, so modify the code comment to reflect the reality and remove the useless duplicate declartion in arch/mips/kernel/setup.c. Signed-off-by:
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Tiezhu Yang authored
Fix the following checkpatch error: ERROR: do not initialise globals to 0 #834: FILE: arch/mips/kernel/setup.c:834: +int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ Signed-off-by:
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- 20 Apr, 2020 6 commits
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Jiaxun Yang authored
This driver is using some dangerous hack to set MMIO address for HPET, which might break systems with other kinds of PCH. Also, as Loongson-3 cpufreq driver never appeared in mainline, this driver rarely got used. So we temporarily mark it as broken until we find a better solution. Signed-off-by:
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Jiaxun Yang authored
Add ACPI Controller Node for RS780E PCH to fit newly added driver. Signed-off-by:
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Jiaxun Yang authored
This controller is attached under ISA Bus and can be found in Loongson-3 systems with RS780E PCH. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Jiaxun Yang authored
Make RS780E ACPI as a platform driver so we can enable it by DeviceTree selectively. Signed-off-by:
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Jiaxun Yang authored
RTC is now enabled by devicetree. So platform code is no longer needed. Signed-off-by:
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Thomas Bogendoerfer authored
IOremap changes caused following build error: arch/mips/alchemy/common/setup.c:99:9: error: implicit declaration of function +‘remap_pfn_range’; did you mean ‘io_remap_pfn_range’? +[-Werror=implicit-function-declaration] Fixed my including linux/mm.h Fixes: d3991572 ("MIPS: cleanup fixup_bigphys_addr handling") Signed-off-by:
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- 19 Apr, 2020 10 commits
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H. Nikolaus Schaller authored
There is a unique MAC address programmed into the eFuses of the JZ4780 chip in the CI20 factory. By using this for initializing the DM9000 Ethernet controller, every CI20 board has an individual - but stable - MAC address and DHCP can assign stable IP addresses. Signed-off-by:
H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by:
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PrasannaKumar Muralidharan authored
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board. It also changes the nemc ranges definition to give the driver access to the efuse registers, which are in the middle of the nemc reg range. Tested-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by:
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Christoph Hellwig authored
Use the generic ioremap_page_range helper instead of reimplementing it. Signed-off-by:
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Christoph Hellwig authored
Neither of these interfaces is anywhere near the fast path. Move them out of line and avoid exposing implementation details to the drivers. Signed-off-by:
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Christoph Hellwig authored
Split out the mips64 ioremap implementation entirely, as it will never use page table based remapping. Signed-off-by:
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Christoph Hellwig authored
There is no reason to have two ioremap with flags interfaces. Merge the historic mips __ioremap_mode into ioremap_prot which is a generic kernel interface. Signed-off-by:
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Christoph Hellwig authored
fixup_bigphys_addr is only provided by the alchemy platform. Remove all the stubs, and ensure we only call it if it is actually implemented. Also don't bother implementing io_remap_pfn_range if we don't have to, and move the remaining implementation to alchemy platform code. Signed-off-by:
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Christoph Hellwig authored
This macro is identical to CONFIG_64BIT, and using a Kconfig variable for the only places that checks them (the ioremap implementation) will simplify later patches in this series. Signed-off-by:
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Christoph Hellwig authored
The txx9 sound driver deends on HAS_TXX9_ACLC, which is only set for three tx49xx SOCs, and thus always has a 64-bit phys_addr_t and resource_size_t. Instead of poking into ioremap internals to work around a potentially too small resource_size_t just add a BUILD_BUG_ON to catch such a case. Signed-off-by:
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Jason Yan authored
Fix the following coccicheck warning: arch/mips/netlogic/xlr/fmn.c:106:2-3: Unneeded semicolon Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
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- 16 Apr, 2020 2 commits
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Arnd Bergmann authored
As platforms are moving to COMMON_CLK in general, loongson2ef stuck out as something that has a private implementation but does not actually use it except for setting the frequency of the CPU itself from the loongson2_cpufreq driver. Change that driver to call the register setting function directly and remove the rest of the stub implementation. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by:
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bibo mao authored
There is typo for macro user_ld if __ASSEMBLY__ is declared, this patch fixes this issue. Signed-off-by:
bibo mao <maobibo@loongson.cn> Signed-off-by:
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- 14 Apr, 2020 5 commits
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Jiaxun Yang authored
It never got used by any driver. Signed-off-by:
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bibo mao authored
Header in directory asm/mach-xilfpga is not used any more. Remove it here, and it passes to compile with xilfpga_defconfig Signed-off-by:
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Mike Rapoport authored
Commit 31168f03 ("mips: drop __pXd_offset() macros that duplicate pXd_index() ones") is correct that pud_index() & __pud_offset() are the same when pud_index() is actually provided, however it does not take into account the __PAGETABLE_PUD_FOLDED case. This has broken MIPS KVM compilation because it relied on availability of pud_index(). Define pud_index() regardless of page table folded. It will evaluate to actual index for 4-level pagetables and to 0 for folded PUD level. Link: https://lore.kernel.org/lkml/20200331154749.5457-1-pbonzini@redhat.comReported-by:
Paolo Bonzini <pbonzini@redhat.com> Signed-off-by:
Mike Rapoport <rppt@linux.ibm.com> Tested-by:
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YueHaibing authored
If TTY and SND is not n, we got this warnings: WARNING: unmet direct dependencies detected for HAS_TXX9_SERIAL Depends on [n]: TTY [=n] && HAS_IOMEM [=y] Selected by [y]: - SOC_TX3927 [=y] WARNING: unmet direct dependencies detected for HAS_TXX9_SERIAL Depends on [n]: TTY [=n] && HAS_IOMEM [=y] Selected by [y]: - SOC_TX4938 [=y] Only dependencies is enabled, they can be enabled, so use 'imply' instead of 'select' to fix this. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Tiezhu Yang authored
When I update the mainline kernel on the Loongson 2-way platform which has 8 CPUs, it only shows 4 CPUs due to NR_CPUS is 4, this is obviously wrong. In order to support more CPUs on the Loongson platform, it is better to use CONFIG_NR_CPUS_DEFAULT_64 instead of CONFIG_NR_CPUS_DEFAULT_4 to specify the maximum number of CPUs which the kernel will support. Signed-off-by:
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- 12 Apr, 2020 3 commits
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Linus Torvalds authored
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Linus Torvalds authored
This sorts the actual field names too, potentially causing even more chaos and confusion at merge time if you have edited the MAINTAINERS file. But the end result is a more consistent layout, and hopefully it's a one-time pain minimized by doing this just before the -rc1 release. This was entirely scripted: ./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS --order Requested-by:
Joe Perches <joe@perches.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Linus Torvalds authored
They are all supposed to be sorted, but people who add new entries don't always know the alphabet. Plus sometimes the entry names get edited, and people don't then re-order the entry. Let's see how painful this will be for merging purposes (the MAINTAINERS file is often edited in various different trees), but Joe claims there's relatively few patches in -next that touch this, and doing it just before -rc1 is likely the best time. Fingers crossed. This was scripted with /scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS but then I also ended up manually upper-casing a few entry names that stood out when looking at the end result. Requested-by:
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