- 04 Jun, 2014 9 commits
-
-
Jani Nikula authored
Generated using semantic patches: @@ expression E; @@ - drm_get_encoder_name(&E) + E.name @@ expression E; @@ - drm_get_encoder_name(E) + E->name v2: Turn drm_get_encoder_name(&E) into E.name instead of &(E)->name. Acked-by:
David Herrmann <dh.herrmann@gmail.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
-
Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name [airlied: regenerated] Acked-by:
-
Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name [airlied: regenerated] Acked-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
-
Jani Nikula authored
Generated using semantic patches: @@ expression E; @@ - drm_get_connector_name(&E) + E.name @@ expression E; @@ - drm_get_connector_name(E) + E->name v2: Turn drm_get_connector_name(&E) into E.name instead of &(E)->name. Acked-by:
-
Jani Nikula authored
Generated using semantic patches: @@ expression E; @@ - drm_get_connector_name(&E) + E.name @@ expression E; @@ - drm_get_connector_name(E) + E->name v2: Turn drm_get_connector_name(&E) into E.name instead of &(E)->name. Acked-by:
-
Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name Acked-by:
-
David Mansfield authored
spice-server and downstream code expect that the primary surface will always have surface_id = 0, while in reality, once allocated, the surface_id in qxl.ko is NEVER 0. In a dual head environment, all monitors render portions of the primary surface. However, when the monitor config events are generated and sent, the primary surface is only mapped to the correct identifier (i.e. 0) for the primary head (where crtc index is 0). The fix is to look at the "primary" flag in the bo and always use id 0, irrespective of which head is being configured. [airlied: qxl hw really needs to be fixed to scanout surfaces] Signed-off-by: -
Christian König authored
Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling v4: update crtc->primary->fb when the flip actually happens Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Dave Airlie authored
This reverts commit 1aab5514. Apply the fixed up version instead.
-
- 03 Jun, 2014 1 commit
-
-
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Highlights: - GPUVM opimtizations - HDMI audio cleanups - Deep color HDMI support - more bug fixes, cleanups * 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits) drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color. drm/edid: Parse and handle HDMI deep color modes. drm/radeon: Limit hdmi deep color bit depth to 12 bpc. drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2) drm/radeon: fix pll setup for hdmi deep color (v7) drm/radeon: use hw cts/n values for deep color drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi drm/radeon/atom: fix dithering on certain panels drm/radeon: optimize CIK VM handling v2 drm/radeon: optimize SI VM handling drm/radeon: add define for flags used in R600+ GTT drm/radeon: rework page flip handling v3 drm/radeon: separate vblank and pflip crtc handling drm/radeon: split page flip and pending callback drm/radeon: remove drm_vblank_get|put from pflip handling drm/radeon: remove (pre|post)_page_flip callbacks drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices drm/radeon: fix typo in radeon_connector_is_dp12_capable() radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770 vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled ...
-
- 02 Jun, 2014 30 commits
-
-
Mario Kleiner authored
The Sony PVM-2541A OLED high precision color display supports both 10 bpc and 12 bpc hdmi deep color input, but its edid does not signal any deep color support. Add a quirk to force it being treated as a 12 bpc panel. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
-
Mario Kleiner authored
Check the HDMI cea block for deep color mode bits. If available, assign the highest supported bpc for a hdmi display, corresponding to the given deep color modes. Signed-off-by:
-
Mario Kleiner authored
DCE-4/5/6 can't support more than 12 bpc deep color over hdmi, so clamp to 12 bpc when a hdmi deep color capable display is connected. This even makes sense on DCE-8+, which could do up to 16 bpc, as driving with more than 12 bpc would only waste video bandwidth as long as we don't support framebuffers with more than 12 bpc depth. On pre-DCE4 we clamp hdmi bit depth to 8 bpc, as those asics don't support hdmi deep color. Signed-off-by:
-
Alex Deucher authored
Program HDMI_CONTROL to send general control packets for hdmi deep color mode signalling at every video frame if bpc > 8. This is only supported on evergreen / DCE-4 and later. v2: rebase Signed-off-by:
-
Alex Deucher authored
Need to adjust the pll up for deep color modes. Additionally, the atom bpc defines were wrong in certain cases. v2: set the adjusted clock to the pll clock for hdmi deep color. This fixes display and audio issues with deep color as reported by Andy Furniss <adf.lists@gmail.com> v3: set crtc_clock as well v4: setcrtcinfo on the adjusted mode v5: just use the adjusted clock for setting the pll v6: only use the adjusted clock for hdmi v7: only DCE5 and DCE6 and bpc > 8 Signed-off-by: -
Alex Deucher authored
I'm not really sure how these should be calculated for deep color. The hw generated values seem to work. Signed-off-by: -
Alex Deucher authored
May fix display issues with non-HDMI displays. Signed-off-by: -
Alex Deucher authored
We need to specify the encoder mode as LVDS for eDP when using the Crtc_Source atom table in order to properly set up the FMT hardware. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73911Signed-off-by:
-
Christian König authored
Fill VM page tables from the GART page table if applicable. v2: fix copy&paste error Signed-off-by:
-
Christian König authored
Fill VM page tables from the GART page table if applicable. Signed-off-by:
-
Christian König authored
Signed-off-by:
-
Christian König authored
Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling Signed-off-by:
-
Christian König authored
Signed-off-by:
-
Christian König authored
Signed-off-by:
-
Christian König authored
We activate the VBLANK irq manually anyway, so this is unnecessary. Signed-off-by:
-
Christian König authored
They are doing the same on all generations anyway. Signed-off-by:
-
Alex Deucher authored
Only DCE5+ asics support DP 1.2. Noticed by ArtForz on IRC. Signed-off-by: -
Alex Deucher authored
We were checking the ext clock rather than the display clock. Noticed by ArtForz on IRC. Signed-off-by: -
Émeric MASCHINO authored
Removes useless quirk a7f465f73363fce409870f62173d518b1bc02ae6 introduced with fdo #7770 as a failed attempt to minimize stability issues with hp zx1 chipset/ ATI FireGL X1 graphics adapter configuration (see http://marc.info/?l=linux-ia64&m=140077543819871&w=2 for details/reason) Signed-off-by:
Émeric MASCHINO <emeric.maschino@gmail.com> Signed-off-by:
-
Alex Deucher authored
Avoids blank screens on muxed systems when runpm is active. bug: https://bugs.freedesktop.org/show_bug.cgi?id=75917Signed-off-by:
-
Michele CURTI authored
Signed-off-by:
Michele Curti <michele.curti@gmail.com> Signed-off-by:
-
Michele CURTI authored
Signed-off-by:
-
Rafał Miłecki authored
Thanks to advanced RE of fglrx we finally know what exactly needs to be handled of AFMT change. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
-
Rafał Miłecki authored
Recent RE efforts revealed ops performed by fglrx during HDMI setup. This mostly adds masks to r/w ops plus few single missing bits. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231Signed-off-by:
-
Rafał Miłecki authored
What initially seemed to be a typo in fglrx (using register 0x740c instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and CRC registers swapped which explains why we needed WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by:
-
Rafał Miłecki authored
DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and DCE 3. The order of setting registers and sets of registers are different. It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they have few differences as well. For now separate DCE 2 and DCE 3 path, so we can work on it without a risk of breaking DCE 3.1+. This has been tested for possible regressions on DCE32 HD4550 (RV710). Signed-off-by:
-
Christian König authored
This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by:
-
Christian König authored
This patch implements support for VRAM page table entry compression. PTE construction is enhanced to identify physically contiguous page ranges and mark them in the PTE fragment field. L1/L2 TLB support is enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly improving TLB utilization for VRAM allocations. Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn. Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS on default settings at 1920x1200 resolution with vsync disabled. See main comment in radeon_vm.c for a technical description. v2 (chk): rebased and simplified. v3 (chk): add missing hw setup v4 (chk): rebased on current drm-fixes-3.15 v5 (chk): fix comments and commit text Signed-off-by:
Jay Cornwall <jay@jcornwall.me> Signed-off-by:
-
Alex Deucher authored
The i2c and aux buses use the same pads so add a mutex to protect access to the pads. Signed-off-by:
-
git://anongit.freedesktop.org/drm-intelDave Airlie authored
- prep refactoring for execlists (Oscar Mateo) - corner-case fixes for runtime pm (Imre) - tons of vblank improvements from Ville - prep work for atomic plane/sprite updates (Ville) - more chv code, now almost complete (tons of different people) - refactoring and improvements for drm_irq.c merged through drm-intel-next - g4x/ilk reset improvements (Ville) - removal of encoder->mode_set - moved audio state tracking into pipe_config - shuffled fb pinning out of the platform crtc modeset callbacks into core code - userptr support (Chris) - OOM handling improvements from Chris, with now have a neat oom notifier which jumps additional debug information. - topdown allocation of ppgtt PDEs (Ben) - fixes and small improvements all over * tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits) drm/i915: Kill private_default_ctx off drm/i915: s/i915_hw_context/intel_context drm/i915: Split the ringbuffers from the rings (3/3) drm/i915: Split the ringbuffers from the rings (2/3) drm/i915: Split the ringbuffers from the rings (1/3) drm/i915: s/intel_ring_buffer/intel_engine_cs drm/i915: disable GT power saving early during system suspend drm/i915: fix possible RPM ref leaking during RPS disabling drm/i915: remove user GTT mappings early during runtime suspend drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk drm/i915: Fix gen2 and hsw+ scanline counter drm/i915: Draw a picture about video timings drm/i915: Improve gen3/4 frame counter drm/i915: Add a small adjustment to the pixel counter on interlaced modes drm/i915: Hold CRTC lock whilst freezing the planes drm/i915: Only discard backing storage on releasing the last ref drm/i915: Wait for pending page flips before enabling/disabling the primary plane drm/i915: grab the audio power domain when enabling audio on HSW+ drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off drm/i915: move bsd dispatch index somewhere better ...
-
