- 17 May, 2018 33 commits
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Feifei Xu authored
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Feifei Xu authored
Same as vega10 for now. Reviewed-by:
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Feifei Xu authored
Set external_rev_id and disable cg,pg for now. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
v2: clean up (Alex) v3: additional cleanups (Alex) v4: drop leftover TODO (Alex) Signed-off-by:
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Feifei Xu authored
v2: squash in updates (Alex) v3: squash in more updates (Alex) Acked-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
v2: squash in updates (Alex) v3: squash in more updates (Alex) Reviewed-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
The same as vega10. Reviewed-by:
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Feifei Xu authored
The same as vega10 for now. Reviewed-by:
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Feifei Xu authored
Initial powerplay support the same as vega10 for now. Reviewed-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
vega20_gpu_info firmware stores gpu configuration for vega20. v2: drop gpu info firmware for vega20 Squash of: drm/amdgpu: Add gpu_info firmware for vega20. drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by:
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Feifei Xu authored
Add vega20 to amd_asic_type enum and amdgpu_asic_name[]. Reviewed-by:
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James Zhu authored
Vega20 uses vce 4.1 engine, all the registers have the same absolute offset with vce 4.0. By adjusting vega20 VCE_BASE, vce 4.1 can reuse vce 4.0 header files. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Feifei Xu authored
This headerfile contains vega20's ip base addresses. v2: squash in MP1_BASE fix Acked-by:
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Feifei Xu authored
In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return zfb_phys_addr if ZFB is enabled. Signed-off-by:
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Feifei Xu authored
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Evan Quan authored
configuration change settings Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
This is needed for vega12 and vega20 which do not support legacy powerstate. With this new framework, the DAL clocks limits can also be honored on these asics. Signed-off-by:
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Feifei Xu authored
Update golden_settings_gc_9_0[]. Signed-off-by:
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Laurent Pinchart authored
Commit 75a07f39 ("drm: rcar-du: Zero-out sg_tables when duplicating plane state") introduced a reference to the alpha field of struct rcar_du_vsp_plane_state that got removed in commit 301a9b8d ("drm/rcar-du: Convert to the new generic alpha property"). The issue stems from the merge of the two commits through separate branches and breaks compilation of the driver. Fix it. Fixes: 75a07f39 ("drm: rcar-du: Zero-out sg_tables when duplicating plane state") Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Tested-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180515174752.28954-1-laurent.pinchart+renesas@ideasonboard.com
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Laurent Pinchart authored
The rcar_du_of_init() function is supposed to be defined as a stub when CONFIG_DRM_RCAR_LVDS is disabled as the rcar_du_of.c file isn't compiled in that case. However, a bug in the configuration option check makes it a stub when CONFIG_DRM_RCAR_LVDS=m as well, which prevents legacy DTs from being fixed at boot time. Fix the configuration option check by using IS_ENABLED. Fixes: 81c0e3dd ("drm: rcar-du: Fix legacy DT to create LVDS encoder nodes") Signed-off-by:
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Stephen Rothwell authored
Fixes: 5ae0283e ("drm/amdgpu: Add userptr support for KFD" Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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- 15 May, 2018 7 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change] Link: https://patchwork.freedesktop.org/patch/msgid/20180515185450.1113-1-alexander.deucher@amd.comSigned-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Last drm/i915 changes for v4.18: - NV12 enabling (Chandra, Maarten) - ICL workarounds (Oscar) - ICL basic DPLL enabling (Paulo) - GVT updates - DP link config refactoring (Jani) - Module parameter to override DMC firmware (Jani) - PSR updates (José, DK, Daniel, Ville) - ICL DP vswing programming (Manasi) - ICL DBuf slice updates (Mahesh) - Selftest fixes and updates (Chris, Matthew, Oscar) - Execlist fixes and updates (Chris) - Stolen memory first 4k fix (Hans de Goede) - wait_for fixes (Mika) - Tons of GEM improvements (Chris) - Plenty of other fixes and improvements (Everyone) - Crappy changelog (Me) Signed-off-by:
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Nayan Deshmukh authored
this patch also effect the amdgpu and etnaviv drivers which use the function drm_sched_entity_init Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Suggested-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
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Dirk Hohndel authored
This is dual licensed under GPL-2.0 or MIT. Signed-off-by:
Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Acked-by:
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Christian König authored
Quite useful to know. Signed-off-by:
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Christian König authored
It is meaningless anyway. v2: remove unused variable (Alex) Signed-off-by:
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Yong Zhao authored
This change prepares for a workaround in amdkfd for a GFX9 HW bug. It requires the control stack memory of compute queues, which is allocated from the second page of MQD gart BOs, to have mtype NC, rather than the default UC. Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
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