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  1. 13 Jul, 2020 3 commits
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  9. 18 Dec, 2019 1 commit
  10. 16 Dec, 2019 1 commit
  11. 11 Sep, 2019 1 commit
    • Stephen Boyd's avatar
      mmc: Remove dev_err() usage after platform_get_irq() · 9a7957d0
      Stephen Boyd authored
      We don't need dev_err() messages when platform_get_irq() fails now that
      platform_get_irq() prints an error message itself when something goes
      wrong. Let's remove these prints with a simple semantic patch.
      
      // <smpl>
      @@
      expression ret;
      struct platform_device *E;
      @@
      
      ret =
      (
      platform_get_irq(E, ...)
      |
      platform_get_irq_byname(E, ...)
      );
      
      if ( \( ret < 0 \| ret <= 0 \) )
      {
      (
      -if (ret != -EPROBE_DEFER)
      -{ ...
      -dev_err(...);
      -... }
      |
      ...
      -dev_err(...);
      )
      ...
      }
      // </smpl>
      
      While we're here, remove braces on if statements that only have one
      statement (manually).
      
      Cc: Ulf Hansson <ulf.hansson@linaro.org>
      Cc: linux-mmc@vger.kernel.org
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      9a7957d0
  12. 10 Jul, 2019 1 commit
  13. 05 Jun, 2019 1 commit
  14. 17 Dec, 2018 3 commits
  15. 16 Jul, 2018 4 commits
  16. 31 May, 2018 1 commit
  17. 02 May, 2018 2 commits
  18. 23 Nov, 2017 1 commit
  19. 30 Oct, 2017 5 commits
    • Arnd Bergmann's avatar
      mmc: sdhci-msm: fix x86 build error · 9ccfa817
      Arnd Bergmann authored
      The __WARN_printf() function is not portable across architectures
      and causes a compile-time error on x86 and others that don't use
      the asm-generic version of asm/bug.h:
      
      drivers/mmc/host/sdhci-msm.c: In function 'sdhci_msm_check_power_status':
      drivers/mmc/host/sdhci-msm.c:1066:4: error: implicit declaration of function '__WARN_printf'; did you mean '__dev_printk'? [-Werror=implicit-function-declaration]
          __WARN_printf("%s: pwr_irq for req: (%d) timed out\n",
          ^~~~~~~~~~~~~
      
      The change that introduced this error, "mmc: sdhci-msm: Add sdhci msm
      register write APIs which wait for pwr irq", likely meant to use
      dev_warn(), so I'm changing over to that.
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      9ccfa817
    • Vijay Viswanath's avatar
      mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr irq · c0309b38
      Vijay Viswanath authored
      Register writes which change voltage of IO lines or turn the IO bus
      on/off require controller to be ready before progressing further. When
      the controller is ready, it will generate a power irq which needs to be
      handled. The thread which initiated the register write should wait for
      power irq to complete. This will be done through the new sdhc msm write
      APIs which will check whether the particular write can trigger a power
      irq and wait for it with a timeout if it is expected.
      The SDHC core power control IRQ gets triggered when -
      * There is a state change in power control bit (bit 0)
        of SDHCI_POWER_CONTROL register.
      * There is a state change in 1.8V enable bit (bit 3) of
        SDHCI_HOST_CONTROL2 register.
      * Bit 1 of SDHCI_SOFTWARE_RESET is set.
      
      Also add support APIs which are used by sdhc msm write APIs to check
      if power irq is expected to be generated and wait for the power irq
      to come and complete if the irq is expected.
      
      This patch requires CONFIG_MMC_SDHCI_IO_ACCESSORS to be enabled.
      Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
      Signed-off-by: default avatarVijay Viswanath <vviswana@codeaurora.org>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      c0309b38
    • Sahitya Tummala's avatar
      mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset · 401b2d06
      Sahitya Tummala authored
      There is a rare scenario in HW, where the first clear pulse could
      be lost when the actual reset and clear/read of status register
      are happening at the same time. Fix this by retrying upto 10 times
      to ensure the status register gets cleared. Otherwise, this will
      lead to a spurious power IRQ which results in system instability.
      Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
      Signed-off-by: default avatarVijay Viswanath <vviswana@codeaurora.org>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      401b2d06
    • Subhash Jadavani's avatar
      mmc: sdhci-msm: fix issue with power irq · c7ccee22
      Subhash Jadavani authored
      SDCC controller reset (SW_RST) during probe may trigger power irq if
      previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
      enable the power irq interrupt in GIC (by registering the interrupt
      handler), we need to ensure that any pending power irq interrupt status
      is acknowledged otherwise power irq interrupt handler would be fired
      prematurely.
      Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
      Signed-off-by: default avatarVijay Viswanath <vviswana@codeaurora.org>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      c7ccee22
    • Bjorn Andersson's avatar
      mmc: sdhci-msm: Enable delay circuit calibration clocks · 4946b3af
      Bjorn Andersson authored
      The delay circuit used to support HS400 is calibrated based on two
      additional clocks. When these clocks are not available and
      FF_CLK_SW_RST_DIS is not set in CORE_HC_MODE, reset might fail. But on
      some platforms this doesn't work properly and below dump can be seen in
      the kernel log.
      
        mmc0: Reset 0x1 never completed.
        mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
        mmc0: sdhci: Sys addr:  0x00000000 | Version:  0x00001102
        mmc0: sdhci: Blk size:  0x00004000 | Blk cnt:  0x00000000
        mmc0: sdhci: Argument:  0x00000000 | Trn mode: 0x00000000
        mmc0: sdhci: Present:   0x01f80000 | Host ctl: 0x00000000
        mmc0: sdhci: Power:     0x00000000 | Blk gap:  0x00000000
        mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000002
        mmc0: sdhci: Timeout:   0x00000000 | Int stat: 0x00000000
        mmc0: sdhci: Int enab:  0x00000000 | Sig enab: 0x00000000
        mmc0: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000000
        mmc0: sdhci: Caps:      0x742dc8b2 | Caps_1:   0x00008007
        mmc0: sdhci: Cmd:       0x00000000 | Max curr: 0x00000000
        mmc0: sdhci: Resp[0]:   0x00000000 | Resp[1]:  0x00000000
        mmc0: sdhci: Resp[2]:   0x00000000 | Resp[3]:  0x00000000
        mmc0: sdhci: Host ctl2: 0x00000000
        mmc0: sdhci: ============================================
      
      Add support for the additional calibration clocks to allow these
      platforms to be configured appropriately.
      
      Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org>
      Cc: Ritesh Harjani <riteshh@codeaurora.org>
      Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Tested-by: default avatarJeremy McNicoll <jeremymc@redhat.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      4946b3af