- 15 Aug, 2017 40 commits
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Alex Deucher authored
May waste a bit of memory, but simplifies the interface significantly. v2: convert internal accounting to use 256bit slots Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jean Delvare authored
There are no external users of function amdgpu_atif_handler so it can be static. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Signed-off-by:
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Jean Delvare authored
There are no external users of function radeon_atif_handler so it can be static. Signed-off-by:
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Jean Delvare authored
Include a missing header to get rid of the following warning: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:65:6: warning: no previous prototype for ‘amdgpu_pm_acpi_event_handler’ [-Wmissing-prototypes] void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) ^ Signed-off-by: -
Jean Delvare authored
Include a missing header to get rid of the following warning: drivers/gpu/drm/amd/amdgpu/dce_v6_0.c:521:6: warning: no previous prototype for 'dce_v6_0_disable_dce' [-Wmissing-prototypes] void dce_v6_0_disable_dce(struct amdgpu_device *adev) ^ Signed-off-by: -
Jean Delvare authored
As I was staring at the si_init_golden_registers code, I noticed that the Pitcairn initialization silently falls through the Cape Verde initialization, and the Oland initialization falls through the Hainan initialization. However there is no comment stating that this is intentional, and the radeon driver doesn't have any such fallthrough, so I suspect this is not supposed to happen. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Alex Deucher authored
Move it up before ring enablement with all of the other engine setup and explicitly disable it for bare metal. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by:
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Alex Deucher authored
We already allocate this as part of the ring structure, use that instead. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by:
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Alex Deucher authored
The wb buffer is in system memory, not vram so the flush is useless. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by:
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Alex Deucher authored
No functional change until wptr polling uses this location (future patch). v2: use WRITE_ONCE Cc: Frank Min <Frank.Min@amd.com> Reviewed-by:
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Felix Kuehling authored
kfd2kgd is device-specific, so it should not be a global variable. Merge amdgpu_amdkfd_load_interface and amdgpu_amdkfd_device_probe so that it's only needed as a local variable in one function. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
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Junwei Zhang authored
Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Alex Deucher authored
nbio registers are not used in this file. Reviewed-by:
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Alex Deucher authored
The gfxhub and mmhub code are now helpers for gmc rather than standalone IPs. When that changes these were left over. Remove them. Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Alex Deucher authored
Use a lower case b to be consistent with the other wb functions. Reviewed-by:
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Yong Zhao authored
We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for PDEs and setting S bit to 1 for PTEs when the corresponding addresses are not occupied by gpu driver allocated buffers. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
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Yong Zhao authored
The parameter init_value contains the value to which we initialized VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set. Signed-off-by:
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Christian König authored
Saves us even more loc. Signed-off-by:
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Christian König authored
Saves us quite a bunch of loc. Signed-off-by:
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Christian König authored
Same as amdgpu_bo_create_kernel, but keeps the BO reserved. Signed-off-by:
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Christian König authored
Make allocating the new BO optional. Signed-off-by:
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Christian König authored
Save some memory because only one of those is used at all times. Signed-off-by:
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Christian König authored
Move amdgpu_bo and related structures into amdgpu_object.h. Move amdgpu_bo_list structures to the amdgpu_bo_list functions. Signed-off-by:
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Christian König authored
Instead of open coding the conversion from u64 to pointers. Signed-off-by:
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Christian König authored
Don't keep around the same pointer twice. Signed-off-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Signed-off-by:
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Evan Quan authored
Signed-off-by:
Ken Wang <ken.wang@amd.com> Reviewed-by:
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Rex Zhu authored
In some asics,Really no need to program PCC HW register. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Frank Min authored
While doing flr on VFs, there is possibility to lost the doorbell writing for sdma, so enable poll mem for sdma, then sdma fw would check the pollmem holding wptr. Signed-off-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by:
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Frank Min authored
1.Since in sriov there is no need of decoding, so skip the related code; 2.Vcpu boot up and umc enable need to take at the end of the init sequence; Signed-off-by:
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Frank Min authored
Optimize init table sequence for sriov. Signed-off-by:
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Frank Min authored
Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff Signed-off-by:
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Frank Min authored
Since rptr would not be accessed on later secure asics in sriov, remove the ring test. Signed-off-by:
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Frank Min authored
Interrupt enable is contained in vce init table and this register could not be accessed in secure ASICs, so just remove it. Signed-off-by:
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Frank Min authored
Add uvd and vce re-init after gpu reset. Signed-off-by:
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Frank Min authored
MMSCH FW need to get the wptr from 0 after it get the mailbox request from driver, since every time kick the mailbox, mmsch thinks that it is the first time engine start to initialize. Signed-off-by:
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Yong Zhao authored
That function will be used later to support setting a page table block with 64 bit value. Signed-off-by:
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Leo Liu authored
The dpm control for vcn has been moved to firmware, kernel always spins "amdgpu: [powerplay] pp_dpm_powergate_uvd was not implemented", each time when application runs, disable it for now till pg/cg. Also remove clock manual setting when dpm disabled, which was inherited from uvd. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Xiangliang.Yu authored
Vega10 also support virtual display, remove the error message. Signed-off-by:
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