An error occurred fetching the project authors.
- 25 Feb, 2020 1 commit
-
-
Wyatt Wood authored
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Add infrastructure to enable and disable PSR on DMCUB. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
- 06 Feb, 2020 2 commits
-
-
Isabel Zhang authored
[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
-
Eric Yang authored
[Why] Previous logic is only good for 15W parts. Other configuration need a smarter logic to match clk levels with pp table in the fuse. [How] Cache all 8 DPM level's clock data, find lvl that match each pstate in the pp table and build input into DML base on that Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
-
- 22 Jan, 2020 1 commit
-
-
Isabel Zhang authored
[Why] MPO isn't enabled on some 4k videos due to video source width is 4096 and the current limit is 3840. [How] Changed the limit to 4096. Signed-off-by:
-
- 16 Jan, 2020 6 commits
-
-
Sung Lee authored
[Why] DML Initialization was previously done on dcn21_resource initialization. This meant that DML soc struct was populated with hardcoded values. [How] Move DML initialization to after updating bounding box, to use clock table values from SMU. Signed-off-by:
-
George Shen authored
[Why] PHY will sometimes be in bad state on hotplugging display from USB-C dongle. [How] Add additional calls to disable and then enable PHY before link training starts during verify_link_cap. Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
-
Noah Abradjian authored
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
-
Wyatt Wood authored
[Why] Moving PSR from DMCU to DMCUB. [How] Add driverside PSR changes required to send inbox messages to fw. These changes are non-functional until the psr structure allocation is uncommented. Signed-off-by:
-
Noah Abradjian authored
[Why] When rapidly adjusting video brightness, screen tearing was observed. This was due to overwritten values in ICSC registers. In dcn10, this issue had been fixed by implementing double buffering via alternating ICSC modes. However, the second register set used in dcn1 doesn't exist in dcn2. [How] Create new program_input_csc for dcn20. Use ICSC_B registers instead of COMA registers as second set. Signed-off-by:
-
Noah Abradjian authored
[Why] When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed. This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by implementing double buffering by alternating OCSC modes. [How] Alternate which OCSC registers are used by switching modes each time. This double buffers the CSC writes. Signed-off-by:
-
- 18 Dec, 2019 6 commits
-
-
abdoulaye berthe authored
[Why] DCN21 and DCN2 extended timeout support cap is not set correctly. [How] Set extended timeout support for ASIC families to their right values. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
-
Sung Lee authored
[Why] Previously update_bw_bounding_box for RN was commented out due to incorrect values causing BSOD on Hybrid Graphics. However, commenting out this function also may cause issues such as underflow in certain cases such as 2x4K displays. [How] Fix dram_speed_mts calculations. Update from proper index of clock_limits[] Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
-
Noah Abradjian authored
[Why] Currently, pipe resources are assigned to an index that matches the pipe position. However, if pipe 1 or 2 is disabled, there will be a gap in the arrays which causes a crash when iterating based on pipe_count. [How] Fix resource construct to assign resources to minimum available array index. Signed-off-by:
-
abdoulaye berthe authored
Signed-off-by:
-
Roman Li authored
[Why] The earlier change: "check phy dpalt lane count config" uses link encoder registers not defined properly. That caused regression with mst-enabled display not lighting up. [How] Add missing reg definitions. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
-
Timothy Pearson authored
Introduce DC_FP_START()/DC_FP_END() macros to help enable floating point kernel mode support across various architectures. v2: move copyright update to commit which adds the changes Signed-off-by:
Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by:
-
- 11 Dec, 2019 1 commit
-
-
Arnd Bergmann authored
Calling kzalloc() and related functions requires the linux/slab.h header to be included: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 'dcn21_ipp_create': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? [-Werror=implicit-function-declaration] kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); A lot of other headers also miss a direct include in this file, but this is the only one that causes a problem for now. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
-
- 10 Dec, 2019 1 commit
-
-
Arnd Bergmann authored
Calling kzalloc() and related functions requires the linux/slab.h header to be included: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 'dcn21_ipp_create': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? [-Werror=implicit-function-declaration] kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); A lot of other headers also miss a direct include in this file, but this is the only one that causes a problem for now. Signed-off-by:
-
- 05 Dec, 2019 6 commits
-
-
Eric Yang authored
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
-
Joseph Gravenor authored
[why] pstate_latency_us never gets updated from the hard coded value in rn_clk_mgr.c [how] update the wm table's values before we do calculations with them Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
-
Eric Yang authored
[Why] DF team has produced more optimized latency numbers. [How] Add sr latencies to the wm table, use different latencies for different wm sets. Also fix bb override from registery key for these latencies. Signed-off-by:
-
Eric Yang authored
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by:
-
Joseph Gravenor authored
[why] pstate_latency_us never gets updated from the hard coded value in rn_clk_mgr.c [how] update the wm table's values before we do calculations with them Signed-off-by:
-
Eric Yang authored
[Why] DF team has produced more optimized latency numbers. [How] Add sr latencies to the wm table, use different latencies for different wm sets. Also fix bb override from registery key for these latencies. Signed-off-by:
-
- 19 Nov, 2019 3 commits
-
-
Anthony Koo authored
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions [How] 1. Make function pointer table init in its own init.c file 2. Remove other scenarios in hwseq.c file that need to include headers of other DCN versions. (If needed, it should have been done via the function pointers) Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
-
Anthony Koo authored
[Why] Too many construct functions which makes searching difficult, especially on some debuggers. [How] Append all construct and destruct functions with dcn number and object type to make each construct function name unique Signed-off-by:
-
Alvin Lee authored
Changes in dc to allow for different cases where full update is required. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
- 13 Nov, 2019 7 commits
-
-
Bhawanpreet Lakha authored
[Why] DCN21 is stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup Renoir definitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN21 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: -
Bhawanpreet Lakha authored
[Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: -
Eric Yang authored
[Why] For unknown reason, immediate flip with host VM translation on NV12 surface will underflow on last row of PTE. [How] Hack chroma viewport height to make fetch one more row of PTE. Note that this will cause hubp underflow on all video underlay cases, but the underflow is not user visible since it is in blank region. Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] Support for DMUB only depends on support for DC. It doesn't use floating point so we don't need to guard it by any specific DCN revision. [How] Drop the guards and cleanup the newlines around each one. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
-
Nicholas Kazlauskas authored
DC will use DMUB for command submission and flow control during initialization. Register offloading as well as submitting some BIOS commands are part of the DC internal interface but are guarded behind debug options. It won't be functional in amdgpu_dm yet since we don't pass the DMUB service to DC for use. Signed-off-by:
-
Yongqiang Sun authored
[Why] DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize sequence. [How] Change dmcu init sequece to meet dmcub initilize. Signed-off-by:
-
Nicholas Kazlauskas authored
The interface to the DMCUB won't be through DC itself. DC will instead call into the DMUB interface introduced with a future change. The CONFIG_DRM_AMD_DC_DMUB defines will still be used for now but will be dropped at the end of the series. Since this define was never configurable in the first place this code wasn't used. Signed-off-by:
-
- 25 Oct, 2019 6 commits
-
-
Eric Yang authored
[Why] Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A. Was not filled in. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
-
Sung Lee authored
[Why] In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP. This causes an issue on dc init where dcn2_1_soc which has been updated by update_bw_bounding_box gets put into dml->soc. As update_bw_bounding_box is currently incorrect for dcn2.1, this makes dml calculations fail due to incorrect parameters, leading to a crash on PnP. [How] Comment out update_bw_bounding_box call for now. Signed-off-by:
-
Michael Strauss authored
[WHY] force_single_disp_pipe_split is a debug flag for use on DCN1 but isn't necessary otherwise as DCN2+ splits by default Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
-
Yogesh Mohan Marimuthu authored
[Why] The enum value for TRANSMITTER_UNIPHY_G is 9. In resource dc_xx_resource file structure link_enc_regs[], the TRANSMITTER_UNIPHY_G registers are initialized at index 6. Due to this mismatch, if monitor is attached to port using TRANSMITTER_UNIPHY_G then the monitor blanks out. [How] add function map_transmitter_id_to_phy_instance() and use the function to map enum transmitter to link regs. Signed-off-by:
Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by:
-
Yongqiang Sun authored
[Why & How] vm should be enabled by default for rn to get right dml. Signed-off-by:
-
Michael Strauss authored
[WHY] DML is incorrectly initialized with 4 pipes on 3 pipe configs RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display) [HOW] Set correct number of DPP/OTGs for dml init to generate correct DPP topology Double RequiredDPPCLK after clock is halved for pipe split and find_secondary_pipe fails to fix underflow Signed-off-by:
-
