- 18 May, 2011 2 commits
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Jesse Barnes authored
It's not used on Ironlake, but is used on later generations, so make sure it exists before we try to use it in the interrupt handlers. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
Keith Packard <keithp@keithp.com> Signed-off-by:
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Chris Wilson authored
The ddc proxy depends upon the underlying i2c bus being selected. Under certain configurations, the i2c-adapter functionality is queried during initialisation and so may trigger an OOPS during boot. Hence, we need to reorder the initialisation of the ddc proxy until after we hook up the i2c adapter for the SDVO device. The condition under which it fails is when the i2c_add_adapter calls into i2c_detect which will attempt to probe all valid addresses on the adapter iff there is a pre-existing i2c_driver with the same class as the freshly added i2c_adapter. So it appears to depend upon having compiled in (or loaded such a module before i915.ko) an i2c-driver that likes to futz over the i2c_adapters claiming DDC support. Reported-by:
Mihai Moldovan <ionic@ionic.de> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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- 17 May, 2011 3 commits
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Keith Packard authored
Commit 357555c0 split out IVB-specific register definitions for FDI link training, but a piece of that commit stopped executing some critical code on Ironlake systems while leaving it running on Sandybridge. Turn that code back on both Ironlake and Sandybridge Signed-off-by:
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Jesse Barnes authored
With FBC disabled by default, it should be safe to enable RC6. So let's give it a try. Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Jesse Barnes authored
FBC has too many corner cases that we don't currently deal with, so disable it by default so we can enable more important features like RC6, which conflicts in some configurations. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31742Signed-off-by:
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- 16 May, 2011 2 commits
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Feng, Boqun authored
This patch depends on patch "drm/i915: fix user irq miss in BSD ring on g4x". Once the previous patch apply, ring_get_irq/ring_put_irq become unused. So simply remove them. Signed-off-by:
Feng, Boqun <boqun.feng@intel.com> Reviewed-by:
Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by:
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Feng, Boqun authored
On g4x, user interrupt in BSD ring is missed. This is because though g4x and ironlake share the same bsd_ring, their interrupt control interfaces have _two_ differences. 1.different irq enable/disable functions: On g4x are i915_enable_irq and i915_disable_irq. On ironlake are ironlake_enable_irq and ironlake_disable_irq. 2.different irq flag: On g4x user interrupt flag in BSD ring on is I915_BSD_USER_INTERRUPT. On ironlake is GT_BSD_USER_INTERRUPT Old bsd_ring_get/put_irq call ring_get_irq and ring_get_irq. ring_get_irq and ring_put_irq only call ironlake_enable/disable_irq. So comes the irq miss on g4x. To fix this, as other rings' code do, conditionally call different functions(i915_enable/disable_irq and ironlake_enable/disable_irq) and use different interrupt flags in bsd_ring_get/put_irq. Signed-off-by:
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- 14 May, 2011 22 commits
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Jesse Barnes authored
Ibex Peak and CougarPoint already require a different setting (added here), and future chips will likely follow that precedent. Signed-off-by:
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Jesse Barnes authored
Some of the bits have changed, including one we were setting that enables a VGA test mode, preventing pipe B from working at all. So add a new IVB specific function with the right bits. Signed-off-by:
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Eric Anholt authored
They have been moved from the ringbuffer groups to their own group it looks like. Fixes GPU hangs on gnome startup. Signed-off-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
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Eric Anholt authored
The registers are the same as on Sandybridge. Fixes scrambled display in X when it does software drawing to the GTT, and scans the results out as tiled. Signed-off-by:
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Eric Anholt authored
This is once less place to miss a new INTEL_INFO(dev)->gen update now. Signed-off-by:
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Jesse Barnes authored
This helps contain the mess to init_display() instead. Signed-off-by:
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Jesse Barnes authored
This is a little less confusing than relying on the implicit zeroing of the dev_priv. Signed-off-by:
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Jesse Barnes authored
There are several variants, set feature bits appropriately for both mobile and desktop parts. Signed-off-by:
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Jesse Barnes authored
We can treat PantherPoint as CougarPoint as far as display goes. Signed-off-by:
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Jesse Barnes authored
Just use the Sandy Bridge routines. Signed-off-by:
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Jesse Barnes authored
Use Sandy Bridge paths in a few places. Signed-off-by:
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Jesse Barnes authored
Treat Ivy Bridge like previous chips as far as flip submission is concerned. Signed-off-by:
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Jesse Barnes authored
Add new interrupt handling functions for Ivy Bridge. Signed-off-by:
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Jesse Barnes authored
Not fully tested. Signed-off-by:
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Jesse Barnes authored
A0 stepping chips need to use manual training, but the bits have all moved. So fix things up so we can at least train FDI for VGA links. Signed-off-by:
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Jesse Barnes authored
Treat it like Ironlake and Sandy Bridge. Signed-off-by:
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Jesse Barnes authored
Ivy Bridge has a similar split display controller to Sandy Bridge, so use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so use HAS_PIPE_CONTROL as well. Signed-off-by:
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Jesse Barnes authored
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Jesse Barnes authored
Note: IS_GEN* are for render related checks. Display and other checks should use IS_MOBILE, IS_$CHIPSET or test for specific features. Signed-off-by:
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Jesse Barnes authored
This makes the Ironlake+ code trivial and generally simplifies things. Signed-off-by:
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Jesse Barnes authored
Set the IRQ handling functions in driver load so they'll just be used directly, rather than branching over most of the code in the chipset functions. Signed-off-by:
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Jesse Barnes authored
Rather than branching in ironlake_pch_enable, add a new train_fdi function to the display function pointer struct and use it instead. Signed-off-by:
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- 13 May, 2011 1 commit
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Ben Widawsky authored
Forcewake needs to register itself with drm to use the remove function. The file also should be read only. Signed-off-by:
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- 11 May, 2011 1 commit
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Keith Packard authored
Signed-off-by:
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- 10 May, 2011 9 commits
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Ben Widawsky authored
forcewake is controlled by the open and close of the debugfs file. This assures that buggy applications cannot cause the GT to stay on forever. Signed-off-by:
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Ben Widawsky authored
The render P-state handling code requires reading from a GT register. This means that FORCEWAKE must be written to, a resource which is shared and should be protected by struct_mutex. Hence we can not manipulate that register from within the interrupt handling and so must delegate the task to a workqueue. Signed-off-by:
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Ben Widawsky authored
Found by the new strict checking for the mutex being held whilst manipulating the forcewake status. Signed-off-by:
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Ben Widawsky authored
Provide a reference count to track the forcewake state of the GPU and give a safe mechanism for userspace to wake the GT. This also potentially saves a UC read if the GT is known to be awake already. The reference count is atomic, but the register access and hardware wake sequence is protected by struct_mutex. Signed-off-by:
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Ben Widawsky authored
Moved the macros around to properly do reads and writes for the given GPU. This is to address special requirements for gen6 (SNB) reads and writes. Registers in the range 0-0x40000 on gen6 platforms require special handling. Instead of relying on the callers to pick the registers correctly, move the logic into the read and write functions. Signed-off-by:
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Chris Wilson authored
If the outputs are active and continuing to access the GATT when we teardown the PTEs, then there is a potential for us to hang the GPU. The hang tends to be a PGTBL_ER with either an invalid host access or an invalid display plane fetch. v2: Reorder IRQ initialisation to defer until after GEM is setup. Reported-by:
Pekka Enberg <penberg@kernel.org> Signed-off-by:
Rick Bramley <richard.bramley@hp.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35635Reported-and-tested-by:
Zdenek Kabelac <zdenek.kabelac@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36048Reviewed-by:
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Chris Wilson authored
Rely on the GPU snooping into the CPU cache for appropriately bound objects on MI_FLUSH. Or perhaps one day we will have a cache-coherent CPU/GPU package... Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Chris Wilson authored
... to clarify just how we use it inside the driver and remove the confusion of the poorly matching agp_type names. We still need to translate through agp_type for interface into the fake AGP driver. Signed-off-by:
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Ben Widawsky authored
Currently this is only useful for the rc6 stuff. But this would also be useful when I finally get around to the logical context + ppgtt stuff. Signed-off-by:
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