- 27 Aug, 2018 40 commits
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Rex Zhu authored
In function ‘gfx_v9_0_check_fw_write_wait’: warning: enumeration value ‘CHIP_TAHITI’ not handled in switch [-Wswitch] Always add default case in case there is no match Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Christian König authored
Use a fixed number of entities for each hardware IP. The number of compute entities is reduced to four, SDMA keeps it two entities and all other engines just expose one entity. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Move the code into a separate function. Signed-off-by:
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Andrey Grodzovsky authored
The flag will prevent another thread from same process to reinsert the entity queue into scheduler's rq after it was already removewd from there by another thread during drm_sched_entity_flush. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Yintian Tao authored
There is no need for gpu full access for suspend phase1 because under virtualization there is no hw register access for dce block. Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
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Emily Deng authored
To avoid the tlb flush not interrupted by world switch, use kiq and one command to do tlb invalidate. v2: Refine the invalidate lock position. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-and-Tested-by:
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Emily Deng authored
Unify bare metal and sriov, and add firmware checking for reg write and reg wait unify command. Signed-off-by:
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Jun Lei authored
[why] Existing DTN infrastructure in driver is hacky. It uses implicit log names, and also incorrect escape ID. [how] - Implement using generic DTN escape ID. - Move file logging functionality from driver to to script; driver now outputs to string/buffer - Move HWSS debug functionality to separate c file - Add debug functionalty for per-block logging as CSV - Add pretty print in python Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Anthony Koo authored
[Why] During S4/S3 stress test it is possible to resume from S4 without calling mode set on eDP, meaning high level optimization flag is not reset. If this is followed by an S3 resume call, driver will see optimization flag is set and consume it and think backend is powered on when in fact it is not. This results in PHY being off in sequence where S4->Resume->S3->Resume->ApplyOpt->black screen. [How] Move optimization flag to stream instead of a DC flag. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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David Francis authored
[Why] There are two versions of the hw function pointers: one for dce80 and one for all other versions. These paired functions are nearly identical. dce80 and dce100 should not require different i2c access functions. [How] Combine each pair of functions into a single function. Mostly the new functions are based on the dce100 versions as those versions are newer, support more features, and were more maintained. Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Sun peng Li <Sunpeng.Li@amd.com> Acked-by:
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Nikola Cornij authored
Define register for dcn10 for future changes Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Add csc_transform struct to dc_stream_update, and program if set when updating streams Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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David Francis authored
[Why] I2C code did not match dc resource model and was generally unpleasant [How] Move code into new svelte dce_i2c files, replacing various i2c objects with two structs: dce_i2c_sw and dce_i2c_hw. Fully split sw and hw code paths. Remove all redundant declarations. Use address lists to distinguish between versions. Change dce80 code to newer register access macros. Signed-off-by:
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Paul Menzel authored
Improve commit d796d844 (drm/radeon/kms: make hibernate work on IGPs) to only migrate VRAM objects if the Linux kernel is actually built with support for hibernation (suspend to disk). Link: https://bugs.freedesktop.org/show_bug.cgi?id=100941Signed-off-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
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Paul Menzel authored
Improve commit d796d844 (drm/radeon/kms: make hibernate work on IGPs) to only migrate VRAM objects if the Linux kernel is actually built with support for hibernation (suspend to disk). The better solution is to get the information, if this is suspend or hibernate, from `amdgpu_device_suspend()`, but that’s more involved, so apply the simple solution first. Link: https://bugs.freedesktop.org/show_bug.cgi?id=107277Signed-off-by:
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Huang Rui authored
The status field must be 0 after FW is loaded. Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Huang Rui authored
These codes are not used. Signed-off-by:
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Christian König authored
Raven doesn't have an VCE block and so also no buggy VCE firmware. Signed-off-by:
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Rex Zhu authored
After set power ungate state, set clock ungate state before when suspend or fini. Reviewed-by:
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Rex Zhu authored
Unify to set power ungate state at the begin of suspend/fini. Remove the workaround code for gfx off feature in amdgpu_device.c. Reviewed-by:
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Rex Zhu authored
There are no any logical changes here. 1. change function names: amdgpu_device_ip_late_set_pg/cg_state to amdgpu_device_set_pg/cg_state. 2. add a function argument cg/pg_state, so we can enable/disable cg/pg through those functions Reviewed-by:
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SivapiriyanKumarasamy authored
Add gamut remap to dc_stream_update struct, and program if set when updating streams. Signed-off-by:
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Krunoslav Kovac authored
[Why] Recently we fixed HDR static meta using AFMT registers to be treated as fast stream update. Dynamic meta is still being treated as (full) surface update because it touches HUBP and it travels with pipe data. Here we change it to be (fast) stream update. Note, originally we also wanted to redesign here a bit, but without OS level support for true dynamic meta, it's left the same. We are simply using HW that can do dynamic meta to send HDR static meta, I still prefer keeping it in one static meta type then defining dynamic meta types to hold the same info. Once we know how OS interfaces look like, we can do proper design. [How] Move dyn meta update from update_hubp_dpp to commit_planes_do_stream_update Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Krunoslav Kovac authored
[Why] Vesa DPMS tool sends different HDR meta in OS flips without changing output parameters. We don't properly update HDR info frame: - we label HDR meta update as fast update - when updating HW info frame, we only do it if full update [How] It should still be fast update, so when doing HW infoframe update, do it always no matter the update type. Also, don't request passive flip for HDR meta update only without output transfer function or color space changed. Signed-off-by:
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Alvin lee authored
Signed-off-by:
Alvin lee <alvin.lee3@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alvin lee authored
- program infoframe for Stereo - program stereo flip control registers properly v2: Add missing license headers Signed-off-by:
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SivapiriyanKumarasamy authored
Signed-off-by:
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Samson Tam authored
Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Harry Wentland authored
This was missed when pushing public patch for 3e3a40b03847 (drm/amd/display: Updated HDR Static Metadata to directly take info packet raw) This is currently no problem yet since we're not doing HDR on Linux yet. Signed-off-by:
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Anthony Koo authored
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Anthony Koo authored
We only need to register once OS calls the interrupt control. Also, if we are entering static screen mode, disable after ramping is done. Disable shall be done via timer of 2 seconds regardless of ramping complete or not, just to simplify. Also, ramp to mid instead of min, due to better flicker performance... Signed-off-by:
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Anthony Koo authored
Tearing occurred because new VTOTAL MIN/MAX was being programmed too early. The flip can happen within the VUPDATE high region, and the new min/max would take effect immediately. But this means that frame is not variable anymore, and tearing would occur when the flip actually happens. The fixed insert duration should be programmed on the first VUPDATE interrupt instead. Signed-off-by:
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Anthony Koo authored
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Anthony Koo authored
Ignore MSA bit on DP display is usually set during SetTimings, but there was a case where the module thought refresh rate was not valid and ignore MSA bit was not set. Later, a valid refresh rate range was requested but since ignore MSA bit not set, it caused black screen. Issue if with how the module checked for VRR support. Fix up that logic. DM should call new valid_range function to determine if timing is supported. Signed-off-by:
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Anthony Koo authored
This issue occurs if refresh rate range is very small and lfc is not used. When frame spikes occur, refresh rate becomes fixed and will not restore properly Signed-off-by:
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Anthony Koo authored
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Anthony Koo authored
Remove dependency on internal sink map and instead use existing stream and plane state Signed-off-by:
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Harry Wentland authored
Add code to tear down freesync modules when disabled. Signed-off-by:
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Feifei Xu authored
With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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