- 21 Dec, 2013 1 commit
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Mark Brown authored
Make it easier to notice the common file for ChromeOS devices based on the Exynos5250 by giving it the exynos5250 prefix that the boards have. Signed-off-by:
Mark Brown <broonie@linaro.org> Acked-by:
Tomasz Figa <t.figa@samsung.com> Reviewed-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- 20 Dec, 2013 20 commits
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Mark Brown authored
Ensure that unused I2C controllers are not activated, causing problems due to inappropriate pinmuxing or similar, by marking the controllers as disabled by default and requiring boards to explicitly enable those that are in use. Signed-off-by:
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Mark Brown authored
Rather than requiring each board to explicitly disable the SPI controllers it is not using instead require boards to enable those that they are using. This is less work overall since normally at most one of the controllers is in use and avoids issues caused by inappropriate pinmuxing. Signed-off-by:
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Mark Brown authored
There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add this to the device tree bindings. Signed-off-by:
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Naveen Krishna Chatradhi authored
Exynos5420 SoC has per core thermal management unit. 5 TMU channels 4 for CPUs and 5th for GPU. This patch adds the device tree nodes to the DT device list. Nodes carry the misplaced second base address and the second clock to access the misplaced base address. Signed-off-by:
Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by:
Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
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Yuvaraj Kumar C D authored
Commit e908d5c5 ("ARM: dts: change status property of dwmmc nodes for exynos5250") missed out handling the exynos5250 snow dts file. Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by:
Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by:
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Tomasz Figa authored
For consistency with other device tree nodes, this patch adds missing spaces after node labels. Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Tomasz Figa authored
There is no need to use two cells for interrupt specifiers inside the MCT interrupt map, so this patch simplifies the map to use one cell. Signed-off-by:
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Tomasz Figa authored
For MCT block compatible with "samsung,exynos4412-mct", that uses PPI interrupts for local timers, only one local interrupt needs to be specified, since it is a per-processor interrupt. This allows moving MCT node of Exynos4x12 SoCs back to common exynos4x12.dtsi, since they have the same set of interrupts to be specified, which was the only difference. Signed-off-by:
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Tomasz Figa authored
MCT is not an interrupt controller and so there is no point for device tree nodes representing it to contain interrupt-controller and #interrupt-cells properties. Signed-off-by:
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Tomasz Figa authored
This patch updates description of device tree bindings for Exynos MCT (multicore timers). Namely: - added note about simplified specification of local timer interrupts, when using single per-processor interrupt for all local timers, - changed first example that was incorrectly suggesting that global timer interrupts are optional, - simplified example interrupt map, - added example showing simplified local timer interrupt specification. Signed-off-by:
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Leela Krishna Amudala authored
Add the device-tree binding for the PWM controller to Exynos5250 and Exynos5420 Signed-off-by:
Olof Johansson <olofj@chromium.org> Signed-off-by:
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Leela Krishna Amudala authored
Add SPI device tree nodes to Exynos5420 SoC Signed-off-by:
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Padmavathi Venna authored
This patch adds dma controller node info on Exynos5420. Exynos5420 has adma for audio IPs. As adma clk is dependent on audss clk provider that will be added later. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Signed-off-by:
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Kukjin Kim authored
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Tomasz Figa authored
This patch removes device tree node of SDHCI0 controller and replaces it with MSHC to enable support MMC 4.4 and improve performance of eMMC memory. Signed-off-by:
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Tomasz Figa authored
All SoCs from Exynos4x12 series contain the MSHC block, so its node can be located in exynos4x12.dtsi. In addition, missing clock specifiers are added, generic SoC attributes are moved from board dts files to common dtsi file of SoC family and the node is renamed to a more generic name to follow node naming recommendations. Signed-off-by:
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Seungwon Jeon authored
Clock lookup information is required as driver can manipulate clock rate properly. Signed-off-by:
Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by:
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Tomasz Figa authored
The clock was missing CLK_SET_RATE_PARENT flag, which caused rate setting failures due to inability of reconfiguration of second divider behind it. Signed-off-by:
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Doug Anderson authored
The device tree sent upstream for exynos5250-snow encoded the search key as CAPSLK. However in all ChromeOS kernels it is L_META. One can certainly have long debates about which it ought to be, but I'm proposing setting it to L_META because: * That's how _all_ ChromeOS kernels do it and will do it. * There is no L_META key on the board, so it's nice to have. * For those people who really want it to be caps lock, they can use xmodmap or somesuch. Signed-off-by:
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Doug Anderson authored
When the exynos5250 device tree was sent upstream the keyboard mapping was missing the 2nd instance of the "\" key. There are two copies of the "\" because it simply has a different row and column on US and non-US keyboards. For more details, see the previous patch in this series: (mkbp: Fix problems with backslash). Signed-off-by:
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- 18 Dec, 2013 1 commit
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Tomasz Figa authored
According to board schematics, for HSMMC1 a GPIO line is used to detect card presence, while currently it is being configured for internal card detect line, which is multiplexed with card detect line of HSMMC0 and thus breaking it. This patch adds proper sdhci platform data setting card detect type to external GPIO and fixing operation of HSMMC0. Signed-off-by:
Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
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- 15 Dec, 2013 13 commits
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Sachin Kamat authored
Added a binding example for reference and updated the node name. While at it also removed the name description as it is not necessary. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by:
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Sachin Kamat authored
Fix the name as per DT node naming convention. - rename the node to syscon which is a more generic name. - append the register value to the node name. Signed-off-by:
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Sachin Kamat authored
Added high speed I2C nodes to Exynos5420 DT file. Signed-off-by:
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Sachin Kamat authored
The minimum recommended ARM voltage for Exynos5250 at 200MHz on Arndale board is 0.9125V. Update accordingly. Signed-off-by:
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Chander Kashyap authored
Exynos5420 is octa-core SoC from Samsung. Hence populate all the CPU node entries. Signed-off-by:
Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by:
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Chander Kashyap authored
Exynos5420 is octa-core SoC from Samsung. Hence extend exynos-mct clocksource driver to support 8 local interrupts. Also extend dts entries for 8 interrupts. Signed-off-by:
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Leela Krishna Amudala authored
Adds G-Scaler device nodes to the DT device list Signed-off-by:
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Yuvaraj Kumar C D authored
This patch adds the mmc device tree node entries for exynos5420 SOC. Exynos5420 has a different version of DWMMC controller,so a new compatible string is used to distinguish it from the prior SOC's. Signed-off-by:
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Yuvaraj Kumar C D authored
This patch rename's the device tree mmc node's from "dwmmc" to "mmc". According to ePAPR chapter 2.2.2 generic node name recommendation, it has been opted change from dwmmc to mmc.Also this patch remove the instance index from the node name. Signed-off-by:
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Yuvaraj Kumar C D authored
As fifo-depth property in dw_mmc device tree node is SOC specific, move this property to exynos5250 SOC specific file. Signed-off-by:
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Sachin Kamat authored
As per the timing information for supported panel, the value should be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate. Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152 Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683 Target pixel clock rate for refresh rate @60 Hz = 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz Signed-off-by:
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Tushar Behera authored
As per the timing information for supported panel, the value should be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate. Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152 Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683 Target pixel clock rate for refresh rate @60 Hz = 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
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Yuvaraj Kumar C D authored
According to ePAPR, chapter 2.3.4, the status property has defined that it should be set to "disabled" when "the device is not presently operational, but it might become operational in the future". So this patch disable dwmmc node by "status = disabled" in SOC dts file and enable dwmmc node by "status = okay" in board specific dts file. Signed-off-by:
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- 11 Dec, 2013 3 commits
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Sachin Kamat authored
Fixed samaung -> samsung in property name. Signed-off-by:
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Sachin Kamat authored
Added missing clock frequency property to CPU node to avoid boot time warnings. Signed-off-by:
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Sachin Kamat authored
Though the default value is 1, add it explicitly to avoid unnecessary boot warnings and for consistency. Signed-off-by:
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- 01 Dec, 2013 2 commits
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Alexander Shiyan authored
When CONFIG_S3C_BOOT_UART_FORCE_FIFO symbol is set, we should enable FIFO but actually switch command is missing in the code. This patch adds this switching. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Reviewed-by:
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Yuvaraj Kumar C D authored
Exynos5 series SOC's 5250 and 5420 have different versions of DWMMC controller.So there is a new compatible string to distinguish between them.So these nodes should be moved out of Exynos5 series common device tree source to SOC specific device tree source. Signed-off-by:
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