- 08 Aug, 2016 40 commits
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Ken Wang authored
Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Ken Wang authored
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Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
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Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Flora Cui authored
V2: fix the return value for fill failure and validate bo before filling data Reviewed-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Flora Cui authored
so that bo could be set to some pattern Signed-off-by:
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Alex Deucher authored
This got leftover somehow when I cleaned this up. Reviewed-by:
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Eric Huang authored
Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
It's already covered by the default case, but add it for consistency. Reviewed-by:
Alexandre Demers <alexandre.f.demers@gmail.com> Reviewed-by:
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Alex Deucher authored
Looks like this got missed when we ported the code from radeon. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Tom St Denis authored
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Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
Enable the PG_EN bit just before the SMU would be tasked with the PG transition. Signed-off-by:
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Tom St Denis authored
There's no need to track CG state anymore. Signed-off-by:
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Tom St Denis authored
This is handled properly by both DPM and PP externally. Signed-off-by:
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Tom St Denis authored
Adds support for PM locks around access to registers that might have race conditions on PG transistions. Signed-off-by:
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Tom St Denis authored
This adds a mutex lock for both DPM/PP around the changes in power gating state so that userspace can poll registers without a race condition on power state. Signed-off-by:
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Alex Deucher authored
Now that the implementation is complete. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Huang Rui authored
This patch adds DPM running checking back, because the DPM issue is fixed. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
This patch adds the deep sleep initialization at DPM, it needs send a message to SMC to enable this feature before enable voltage controller. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
It's able to enable iceland powerplay manually via the module parameter. The default state is disabled. Signed-off-by:
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Huang Rui authored
This patch introduces the iceland HW manager of powerplay which includes HW manager, clockpowergating, thermal, and powertune. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
The system management unit (SMU) is a subcomponent of the northbridge that is responsible for a variety of system and power management tasks during boot and runtime for GPU. In powerplay, it will be used on firmware loading and power task management. This patch adds SMU mananger for iceland. Signed-off-by:
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Huang Rui authored
v2: cleanup headers, add copyright Signed-off-by:
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Christian König authored
Saves us quite a bunch of code. Signed-off-by:
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