- 07 Dec, 2018 4 commits
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Christian König authored
Let's support simultaneous submissions to multiple engines. v2: rename the field to num_shared and fix up all users v3: rebased Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aaron Liu authored
For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin For Picasso && FP5 SOCKET board, we use picasso_rlc.bin Judgment method: PCO AM4: revision >= 0xC8 && revision <= 0xCF or revision >= 0xD8 && revision <= 0xDF otherwise is PCO FP5 Signed-off-by:Aaron Liu <aaron.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by:
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Alex Deucher authored
Check if the MC firmware supports FFC and tell the SMC so mclk switching is handled properly. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Add new messages for polaris. Reviewed-by:
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- 05 Dec, 2018 8 commits
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Sharat Masetty authored
This patch adds two new functions to help client drivers suspend and resume the scheduler job timeout. This can be useful in cases where the hardware has preemption support enabled. Using this, it is possible to have the timeout active only for the ring which is active on the ringbuffer. This patch also makes the job_list_lock IRQ safe. Suggested-by:
Sharat Masetty <smasetty@codeaurora.org> Reviewed-by:
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Sharat Masetty authored
In cases where the scheduler instance is used as a base object of another driver object, it's not clear if the driver can call scheduler cleanup on the fail path. So, Set the sched->thread to NULL, so that the driver can safely call drm_sched_fini() during cleanup. Signed-off-by:
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Wen Yang authored
kfree(NULL) is safe, so removes NULL check before freeing the mem. This patch also fix the ifnullfree.cocci warnings. Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
Wen Yang <wen.yang99@zte.com.cn> CC: Alex Deucher <alexander.deucher@amd.com> CC: christian.koenig@amd.com CC: "David (ChunMing) Zhou" <David1.Zhou@amd.com> CC: David Airlie <airlied@linux.ie> (maintainer:DRM DRIVERS) CC: Lyude Paul <lyude@redhat.com> CC: Rex Zhu <Rex.Zhu@amd.com> CC: Jim Qu <Jim.Qu@amd.com> CC: amd-gfx@lists.freedesktop.org CC: dri-devel@lists.freedesktop.org Signed-off-by:
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Leo Li authored
In particular, we need the mmMC_VM_XGMI_LFB_CNTL register, for determining if xGMI is enabled on VG20. This will be used by DC to determine the correct spread spectrum adjustment for display and audio clocks. Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Alex Deucher authored
SI does not use doorbells, move asic doorbell init later asic check. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=108920Reviewed-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Alex Deucher authored
Adjust limits for newer polaris variants. v2: fix polaris11 kicker (Jerry) Reviewed-by:
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Alex Deucher authored
Update switch limit on newer polaris variants. This may fix flickering with high refresh rates with mclk switching enabled. Reviewed-by:
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David Francis authored
[Why] Tracing is a useful and cheap debug functionality [How] This creates a new trace system amdgpu_dm, currently with three trace events amdgpu_dc_rreg and amdgpu_dc_wreg report the address and value of any dc register reads and writes amdgpu_dc_performance requires at least one of those two to be enabled. It counts the register reads and writes since the last entry v2: Don't check for NULL before kfree Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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- 04 Dec, 2018 1 commit
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Andrey Grodzovsky authored
amdgpu_xgmi_update_topology is called both on device registration and reset. Fix misleading print since the device is added only once to the hive on registration and not on reset. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
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- 03 Dec, 2018 6 commits
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Andrey Grodzovsky authored
Use per hive wq to concurrently send reset commands to all nodes in the hive. v2: Switch to system_highpri_wq after dropping dedicated queue. Fix non XGMI code path KASAN error. Stop the hive reset for each node loop if there is a reset failure on any of the nodes. Signed-off-by:
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Andrey Grodzovsky authored
XGMI hive has some resources allocted on device init which needs to be deallocated when the device is unregistered. v2: Remove creation of dedicated wq for XGMI hive reset. v3: Use the gmc.xgmi.supported flag Signed-off-by:
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Andrey Grodzovsky authored
No point in use mdelay unless running from interrupt context (which we are not) This is busy wait which will block the CPU for the entirety of the wait time. Also, reduce wait time to 500ms as it is done in refernce code because 1s might cause PSP FW TO issues during XGMI hive reset. Signed-off-by:
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Christian König authored
We ignored the return code here. Signed-off-by:
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Christian König authored
It is unused. Signed-off-by:
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Alex Deucher authored
Use this to track whether an asic supports xgmi rather than checking the asic type everywhere. Reviewed-by:
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- 30 Nov, 2018 21 commits
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Fatemeh Darbehani authored
[Why] To prepare for clock debug logging. With the exception of removing max_supported_dppclk_khz from logs, there are no functional changes. [How] Add clk_bypass struct and clean up buffer logic Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Su Chung <Su.Chung@amd.com> Acked-by:
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Steven Chiu authored
Signed-off-by:
Steven Chiu <steven.chiu@amd.com> Reviewed-by:
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David Francis authored
dce100 was set to always pass safe_to_lower = false to the clock manager Thus, on suspend the clocks were not being set to 0 which is incorrect behaviour This was causing s3 resume to blackscreen on intel CPUs with dce100 GPUs attached (Note that the hash in this Fixes: tag is the hash on Alex's tree) Fixes: ae7d8aeb38d7 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") Signed-off-by: -
SivapiriyanKumarasamy authored
Dithering needs to be enabled or disabled as requested. If dc_stream_update->dither_option is non-null, program the FMT blocks. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] When running igt@kms_plane@pixel-format-pipe-* tests the CRC read will time out and the test will fail. This is because the CRTC is duplicated but the crc_enabled parameter isn't copied over to the new dm_crtc_state. CRC reads will time out because amdgpu_dm_crtc_handle_crc_irq will no longer call drm_crtc_add_crc_entry. [How] Copy crc_enabled when duplicating the state. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Chiawen Huang authored
[why] add customizable log with a message input, which is for adding test log in debugging as printf function in ETW. [Usage] EVENT_LOG_CUST_MSG1("TestLog","Hello World %d=0x%x", 123, pDC); Signed-off-by:Chiawen Huang <chiawen.huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nevenko Stupar authored
For more clear usage in future Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
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hersen wu authored
[WHY] fbc is within the data path from memory to dce. while re-configure mc dmif, fbc should be enabled. otherwise, fbc may not be enabled properly. [HOW] before re-configure mc dmif, disable fbc, only after dmif re-configuration fully done, enable fbc again. Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Harmanprit Tatla authored
* Use provided infopacket in stream (if valid) instead of reconstructing in set_vendor_info_packet() * Use proper format for enums * Use dc info packet struct instead Signed-off-by:
Harmanprit Tatla <Harmanprit.Tatla@amd.com> Reviewed-by:
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abdoulaye berthe authored
[Why] Failure to read Detailed Capabilities Info. [How] Read Detailed Capbilities Info 80h-08Fh. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Krunoslav Kovac authored
Use axis instead of axix Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Joshua Aberback authored
[Why] This patch is for use by dm, no need for it in dc. Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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David Francis authored
[Why] There are a lot of unintuitive parts of the dm-dc interface. It would help us if these were documented to provide a common understanding of what they are supposed to do [How] Most of this documentation is stubs, to be filled out more thoroughly by the experts Not every dm-accessible function and struct is mentioned. Simple functions like getters, setters, retain, release, create, destroy can be left unadorned. Signed-off-by:
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Steven Chiu authored
Signed-off-by:
Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by:
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Yogesh Mohan Marimuthu authored
[why] When there are multiple aux transaction in parallel, it is sometime sporadically the aux transaction starts to continuously fail. The aux transaction was failing because the busy bit for the given gpio pin was always set. The busy bit was alway set because the programming sequence to read, modify and write busy bit was not atomic. Due to which when multiple threads are trying to modify the busy bits for their gpio pins in the same integer variable sometimes the busy bits integer variable is written with old data causing failure. [how] Instead of using individual bits to track gpio pins and grouping them to integers, one byte will be allcoated for each gpio pin. Now whenever a gpio pin needs to be set to mark being used, only writing a value of one to that byte is sufficient, other bytes are not impacted. Also no need to have atomicity with bytes unlike with bits. Signed-off-by:
Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by:
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Christian König authored
Instead of delaying that to the first query. Otherwise we could try to use the SDMA for VM updates before the IB tests are done. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Alex Deucher authored
Looks like it was missed when setting support was added. Reviewed-by:
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Alex Deucher authored
They don't have a fan controller. Reviewed-by:
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Oak Zeng authored
When paging queue is enabled, it use the second page of doorbell. The AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the kernel doorbells are in the first page. So with paging queue enabled, the total kernel doorbell range should be original num_doorbell plus one page (0x400 in dword), not *2. Signed-off-by:
Oak Zeng <ozeng@amd.com> Reviewed-by:
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Christian König authored
We need to set the NO_EVICT flag on the ghost object or otherwise we are adding it to the LRU. When it is added to the LRU we can run into a race between destroying and evicting it again. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] With scaling, underscan and abm changes we can end up calling commit_planes_to_stream in commit_tail. This call uses dm_state->context which can be NULL if the commit was a fast update. [How] Use dc_state instead since that can't be NULL unless the system ran out of memory. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108912 Fixes: e64abff2f133 ("drm/amd/display: Use private obj helpers for dm_atomic_state") Signed-off-by:
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