- 29 Aug, 2019 18 commits
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Bhawanpreet Lakha authored
These are the registers used to for the hw sequences for modesetting. Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
These are the registers used to program the clock hw. Acked-by:
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Bhawanpreet Lakha authored
add registers for dcn, clk, and renoir ip offsets v2: header cleanup (Alex) v3: Add DPCS registers (Hersen) Acked-by:
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Prike Liang authored
add the get_dpm_ultimate_freq for supporting different swSMU. -v2: Handle the unsupported clock type and read smc message failed case and return error code. Move the smu12 uclk frequency retrieved logic to renoir ppt. -v3: Use goto clause to handle invalidate clk index. Add the limited tag for smu_get_dpm_uclk to avoid other likewise interface introduced. Signed-off-by:Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Prike Liang authored
Should populate DPM clocks tables during hw init,otherwise will suffer from invalidate table. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Prike Liang authored
There is no driver message to enable/disable feature mask for APU. For the sake of APU reusing swSMU interface and assume APU supports all the feature. Signed-off-by:
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Prike Liang authored
Init SDMA HW base configuration and enable idle INT for rn. Signed-off-by:
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Tianci.Yin authored
Fix compute ring test failure in sriov scenario. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
stolen memory should be fixed in visible region. Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in a DRM_DEBUG_DRIVER debug message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
No need to add new asic cases. This is a sw display implementation, so just drop the error message so when we add new asics, all we have to do is add the virtual dce IP module. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Jean Delvare authored
Comparing adev->family with CHIP constants is not correct. adev->family can only be compared with AMDGPU_FAMILY constants and adev->asic_type is the struct member to compare with CHIP constants. They are separate identification spaces. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Fixes: 62a37553 ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Signed-off-by:
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Jean Delvare authored
The driver does not support these sensors yet and there is no point in creating sysfs attributes which will always return an error. Signed-off-by:
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Monk Liu authored
for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Xiaojie Yuan authored
jpeg pg depends on vcn pg Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
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Hawking Zhang authored
in_suspend flag should be set in amdgpu_device_suspend/resume in pairs, instead of gfx10 ip suspend/resume function. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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- 27 Aug, 2019 15 commits
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Aaron Liu authored
For picasso(adev->pdev->device == 0x15d8)&raven2(adev->rev_id >= 0x8), firmware is sufficient to support gfxoff. In commit 98f58ada, for picasso&raven2, return directly and cause gfxoff disabled. Fixes: 98f58ada ("drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible") Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Masahiro Yamada authored
Since commit 04d5e276 ("drm/amdgpu: Merge amdkfd into amdgpu"), drivers/gpu/drm/amd/amdkfd/Makefile does not contain any syntax that is understood by the build system. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Kai-Heng Feng authored
Needs ATPX rather than _PR3 to really turn off the dGPU. This can save ~5W when dGPU is runtime-suspended. Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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YueHaibing authored
After commit a9f54ce3 ("drm/amd/display: Refactoring VTEM"), there is no caller in tree. Reported-by:
Hulk Robot <hulkci@huawei.com> Reviewed-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Evan Quan authored
Fix for the commit below: drm/amd/powerplay: implment sysfs feature status function in smu Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Evan Quan authored
Correct the settings for auto mode and skip the unnecessary settings for dcefclk and fclk. Signed-off-by:
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Andrey Grodzovsky authored
Implement HW I2C enigne controller to be used by the RAS EEPROM table manager. This is based on code from ATITOOLs. v2: Rename the file and all function prefixes to smu_v11_0_i2c By Luben's observation always fill the TX fifo to full so we don't have garbadge interpreted by the slave as valid data. v3: Remove preemption disable as the HW I2C controller will not stop the clock on empty TX fifo and so it's not critical to keep not empty queue. Switch to fast mode 400 khz SCL clock for faster read and write. v5: Restore clock gating before releasing I2C bus and fix some style comments. v6: squash in warning fix, fix includes (Alex) Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Luben Tuikov <Luben.Tuikov@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the prevoius hack as the SMU found the bug. v5: Typo fix Signed-off-by:
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Andrey Grodzovsky authored
v3: Merge CKSVII2C_IC regs into exsisting headers. Signed-off-by:
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Andrey Grodzovsky authored
Add RAS EEPROM table manager to eanble RAS errors to be stored upon appearance and retrived on driver load. v2: Fix some prints. v3: Fix checksum calculation. Make table record and header structs packed to do correct byte value sum. Fix record crossing EEPROM page boundry. v4: Fix byte sum val calculation for record - look at sizeof(record). Fix some style comments. v5: Add description to EEPROM_TABLE_RECORD_SIZE and syntax fixes. Signed-off-by:
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Gang Ba authored
This reverts commit 4f8bc72f. It turned out that a single reserved queue wouldn't be sufficient for page fault handling. Signed-off-by:
Gang Ba <gaba@amd.com> Reviewed-by:
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YueHaibing authored
If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28: error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control? dc->hwss.dsc_pg_control = dcn20_dsc_pg_control; ^~~~~~~~~~~~~~~~~~~~ dcn20_dpp_pg_control Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this. Reported-by: -
Dan Carpenter authored
The navi10_message_map[] array has SMU_MSG_MAX_COUNT elements so the ">" has to be changed to ">=" to prevent reading one element beyond the end of the array. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Andrey Grodzovsky authored
Since reservation_object_wait_timeout_rcu is called with interruptable set to false it's wrong to say 'or interrupted' in the error message. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Xiaojie Yuan authored
The GRBM register interface is now capable of bursting 1 cycle per register wr->wr, wr->rd much faster than previous muticycle per transaction done interface. This has caused a problem where status registers requiring HW to update have a 1 cycle delay, due to the register update having to go through GRBM. SW may operate on an incorrect value if they write a register and immediately check the corresponding status register. Registers requiring HW to clear or set fields may be delayed by 1 cycle. For example, 1. write VM_INVALIDATE_ENG0_REQ mask = 5a 2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete 3. write VM_INVALIDATE_ENG0_REQ mask = 5a 4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0 b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because the remote GRBM h/w register takes one extra cycle to be cleared c. In this case, SW will see a false ACK if they exit on first read Affected registers (only GC variant) | Recommended Dummy Read --------------------------------------+---------------------------- VM_INVALIDATE_ENG*_ACK | VM_INVALIDATE_ENG*_REQ VM_L2_STATUS | VM_L2_STATUS VM_L2_PROTECTION_FAULT_STATUS | VM_L2_PROTECTION_FAULT_STATUS VM_L2_PROTECTION_FAULT_ADDR_HI/LO32 | VM_L2_PROTECTION_FAULT_ADDR_HI/LO32 VM_L2_IH_LOG_BUSY | VM_L2_IH_LOG_BUSY MC_VM_L2_PERFCOUNTER_HI/LO | MC_VM_L2_PERFCOUNTER_HI/LO ATC_L2_PERFCOUNTER_HI/LO | ATC_L2_PERFCOUNTER_HI/LO ATC_L2_PERFCOUNTER2_HI/LO | ATC_L2_PERFCOUNTER2_HI/LO Signed-off-by:Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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- 23 Aug, 2019 7 commits
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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hersen wu authored
[WHY] value of dchub_ref_clock is decided by dchubbub global timer settings which is programmed by vbios command table disp_init. for multi-GPU case, vbios is posted only for primary GPU. without vbios posted for the secondary GPU, value of dchub_ref_clock is not set properly. this value will affect dcn bandwidth calcuation and cause underflow. user will see screen flicking during driver installation for dual GPU case. [HOW] dc init_hw always call vbios command table disp_init to make sure dchubbub global timer is configured and enable. Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Joshua Aberback authored
[Why] The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the embedded display. Currently we do not actually read this register's values, so during power down we think that this display is already off, so we skip calling into VBIOS to actually turn it off. [How] - add relevant fields to shift / mask initialization Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Jun Lei authored
[why] Previous workaround to prevent a vsync flip to be converted to immediate flip is no longer needed, and is risky because there are cases where it can result in infinite loop. [how] Remove wait loop (which is potentially infinite) before locking pipe Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Derek Lai authored
[Why] We should be using the ddc_num from res_caps. As the pipe count != number of i2c resources. [How] Use ddc_num from res_cap instead of pipe count. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
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Bayan Zabihiyan authored
[Why] Existing HW Features, HW Diags test requested that the registers be exposed. [How] Add V_TOTAL_MID to existing DC structures. Make sure values are passed down throughout DC Add Register definition. Program the additional registers Add additional Logic for V_TOTAL_CONTROL. Signed-off-by:
Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by:
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Jun Lei authored
[why] Calculating DCFCLK DS time requires calculating delivery time for luma/chroma, but this value is not calculated in DMLv2, it was inadvertently removed when porting DMLv2 [how] Add the calculation back Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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