- 05 Oct, 2015 1 commit
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Sudeep Dutt authored
SCIF depends on IOVA which requires IOMMU_SUPPORT to be enabled. The long term fix is to move IOVA from drivers/iommu to lib/ but this current patch should fix the reported issue. Reported-by:
Fengguang Wu <fengguang.wu@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Sudeep Dutt <sudeep.dutt@intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 04 Oct, 2015 39 commits
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Alexander Shishkin authored
Add myself as a maintainer for the Intel(R) Trace Hub framework and drivers. Signed-off-by:
Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by:
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Alexander Shishkin authored
Parallel Trace Interface (PTI) unit is a trace output device that sends data over a PTI port. The driver provides interfaces to configure bus width, bus clock divider and mode. Tracing is enabled via output device's "active" attribute. Signed-off-by:
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Alexander Shishkin authored
Memory Storage Unit (MSU) is a trace output device that collects trace data to system memory. It consists of 2 independent Memory Storage Controllers (MSCs). This driver provides userspace interfaces to configure in-memory tracing parameters, such as contiguous (high-order allocation) buffer or multiblock (scatter list) buffer mode, wrapping (data overwrite) and number and sizes of windows in multiblock mode. Userspace can read the buffers via mmap()ing or read()ing of the corresponding device node. Signed-off-by:
Laurent Fert <laurent.fert@intel.com> Signed-off-by:
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Alexander Shishkin authored
Software Trace Hub (STH) is a trace source device in the Intel TH architecture, it generates data that then goes through the switch into one or several output ports. STH collects data from software sources using the stm device class abstraction. Signed-off-by:
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Alexander Shishkin authored
Global Trace Hub (GTH) is the central component of Intel TH architecture; it carries out switching between the trace sources and trace outputs, can enable/disable tracing, perform STP encoding, internal buffering, control backpressure from outputs to sources and so on. This property is also reflected in the software model; GTH (switch) driver is required for the other subdevices to probe, because it matches trace output devices against its output ports and configures them accordingly. It also implements an interface for output ports to request trace enabling or disabling and a few other useful things. For userspace, it provides an attribute group "masters", which allows configuration of per-master trace output destinations for up to master 255 and "256+" meaning "masters 256 and above". It also provides an attribute group to discover and configure some of the parameters of its output ports, called "outputs". Via these the user can set up data retention policy for an individual output port or check if it is in reset state. Signed-off-by:
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Alexander Shishkin authored
This patch adds basic support for PCI-based Intel TH devices. It requests 2 bars (configuration registers for the subdevices and STH channel MMIO region) and calls into Intel TH core code to create the bus with subdevices etc. Signed-off-by:
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Alexander Shishkin authored
Intel(R) Trace Hub (TH) is a set of hardware blocks (subdevices) that produce, switch and output trace data from multiple hardware and software sources over several types of trace output ports encoded in System Trace Protocol (MIPI STPv2) and is intended to perform full system debugging. For these subdevices, we create a bus, where they can be discovered and configured by userspace software. This patch creates this bus infrastructure, three types of devices (source, output, switch), resource allocation, some callback mechanisms to facilitate communication between the subdevices' drivers and some common sysfs attributes. Signed-off-by:
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Alexander Shishkin authored
This is a simple stm_source class device driver (kernelspace stm trace source) that registers a console and sends kernel messages over STM devices. Reviewed-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Alexander Shishkin authored
This is a simple module that pretends to be an stm device and discards all the data that comes in. Useful for testing stm class and its users. Reviewed-by:
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Alexander Shishkin authored
Add myself as a maintainer for the stm class framework. Signed-off-by:
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Alexander Shishkin authored
A System Trace Module (STM) is a device exporting data in System Trace Protocol (STP) format as defined by MIPI STP standards. Examples of such devices are Intel(R) Trace Hub and Coresight STM. This abstraction provides a unified interface for software trace sources to send their data over an STM device to a debug host. In order to do that, such a trace source needs to be assigned a pair of master/channel identifiers that all the data from this source will be tagged with. The STP decoder on the debug host side will use these master/channel tags to distinguish different trace streams from one another inside one STP stream. This abstraction provides a configfs-based policy management mechanism for dynamic allocation of these master/channel pairs based on trace source-supplied string identifier. It has the flexibility of being defined at runtime and at the same time (provided that the policy definition is aligned with the decoding end) consistency. For userspace trace sources, this abstraction provides write()-based and mmap()-based (if the underlying stm device allows this) output mechanism. For kernel-side trace sources, we provide "stm_source" device class that can be connected to an stm device at run time. Cc: linux-api@vger.kernel.org Reviewed-by:
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Stephen Boyd authored
Silences this static checker warning: drivers/spmi/spmi-pmic-arb.c:363 pmic_arb_write_cmd() warn: always true condition '(opc <= 255) => (0-255 <= 255)' Cc: Andy Gross <agross@codeaurora.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Stephen Boyd authored
We don't want to swap bytes that we're reading and writing to the FIFOs when we're running on a big-endian CPU. Doing so causes problems like where the qcom-spmi-iadc driver can't detect the type of device because the bytes are all mixed up. Use the raw IO accessors for these API instead, and collapse pmic_arb_base_read() into the byte reading API so that we aren't tempted to read non-FIFO data like commands with that function. Cc: Andy Gross <agross@codeaurora.org> Signed-off-by:
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Philip P. Moltmann authored
Get notified immediately when a balloon target is set, instead of waiting for up to one second. The up-to 1 second gap could be long enough to cause swapping inside of the VM that receives the VM. Acked-by:
Andy King <acking@vmware.com> Signed-off-by:
Xavier Deguillard <xdeguillard@vmware.com> Tested-by:
Siva Sankar Reddy B <sankars@vmware.com> Signed-off-by:
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Philip P. Moltmann authored
Unify the behavior of the first start of the balloon and a reset. Also on unload, declare that the balloon driver does not have any capabilities anymore. Acked-by:
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Philip P. Moltmann authored
2m ballooning significantly reduces the hypervisor side (and guest side) overhead of ballooning and unballooning. hypervisor only: balloon unballoon 4 KB 2 GB/s 2.6 GB/s 2 MB 54 GB/s 767 GB/s Use 2 MB pages as the hypervisor is alwys 64bit and 2 MB is the smallest supported super-page size. The code has to run on older versions of ESX and old balloon drivers run on newer version of ESX. Hence match the capabilities with the host before 2m page ballooning could be enabled. Signed-off-by: -
Philip P. Moltmann authored
When VMware's hypervisor requests a VM to reclaim memory this is preferrably done via ballooning. If the balloon driver does not return memory fast enough, more drastic methods, such as hypervisor-level swapping are needed. These other methods cause performance issues, e.g. hypervisor-level swapping requires the hypervisor to swap in a page syncronously while the virtual CPU is blocked. Hence it is in the interest of the VM to balloon memory as fast as possible. The problem with doing this is that the VM might end up doing nothing else than ballooning and the user might notice that the VM is stalled, esp. when the VM has only a single virtual CPU. This is less of a problem if the VM and the hypervisor perform balloon operations faster. Also the balloon driver yields regularly, hence on a single virtual CPU the Linux scheduler should be able to properly time-slice between ballooning and other tasks. Testing Done: quickly ballooned a lot of pages while wathing if there are any perceived hickups (periods of non-responsiveness) in the execution of the linux VM. No such hickups were seen. Signed-off-by:
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Philip P. Moltmann authored
This helps with debugging vmw_balloon behavior, as it is clear what functionality is enabled. Acked-by:
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Xavier Deguillard authored
Instead of waiting for the next GET_TARGET command, we can react faster by exploiting the fact that each hypervisor call also returns the balloon target. Signed-off-by:
Dmitry Torokhov <dtor@vmware.com> Signed-off-by:
Philip P. Moltmann <moltmann@vmware.com> Acked-by:
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Xavier Deguillard authored
Introduce a new capability to the driver that allow sending 512 pages in one hypervisor call. This reduce the cost of the driver when reclaiming memory. Signed-off-by:
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Geliang Tang authored
Just fix a typo in the code comment. Signed-off-by:
Geliang Tang <geliangtang@163.com> Signed-off-by:
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Sudip Mukherjee authored
If kzalloc() fails then gms is NULL and we are returning NULL, but the functions which called this function gru_register_mmu_notifier() are not expecting NULL as the return. They are expecting either a valid pointer or the error code in ERR_PTR. Signed-off-by:
Sudip Mukherjee <sudip@vectorindia.org> Acked-by:
Dimitri Sivanich <sivanich@sgi.com> Signed-off-by:
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Rickard Strandqvist authored
Remove the function tfh_restart() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by:
Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Acked-by:
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Manuel Schölling authored
To be future-proof and for better readability the time comparisons are modified to use time_before() instead of plain, error-prone math. Signed-off-by:
Manuel Schölling <manuel.schoelling@gmx.de> Acked-by:
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Sudeep Dutt authored
This patch adds the SCIF kernel node QP control messages required to enable SCIF RMAs. Examples of such node QP control messages include registration, unregistration, remote memory allocation requests, remote memory unmap and SCIF remote fence requests. The patch also updates the SCIF driver with minor changes required to enable SCIF RMAs by adding the new files to the build, initializing RMA specific information during SCIF endpoint creation, reserving SCIF DMA channels, initializing SCIF RMA specific global data structures, adding the IOCTL hooks required for SCIF RMAs and updating RMA specific debugfs hooks. Reviewed-by:
Nikhil Rao <nikhil.rao@intel.com> Signed-off-by:
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Sudeep Dutt authored
This patch implements the fence APIs required to synchronize DMAs. SCIF provides an interface to return a "mark" for all DMAs programmed at the instant the API was called. Users can then "wait" on the mark provided previously by blocking inside the kernel. Upon receipt of a DMA completion interrupt the waiting thread is woken up. There is also an interface to signal DMA completion by polling for a location to be updated via a "signal" cookie to avoid the interrupt overhead in the mark/wait interface. SCIF allows programming fences on both the local and the remote node for both the mark/wait or the fence signal APIs. Reviewed-by:
Jacek Lawrynowicz <jacek.lawrynowicz@intel.com> Signed-off-by:
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Sudeep Dutt authored
SCIF allows users to read from or write to registered remote memory via CPU copies or DMA. The API verifies that both local and remote windows are valid before initiating the CPU or DMA transfers. SCIF has optimized algorithms for handling byte aligned as well as cache line aligned DMA engines. A registration cache is maintained to avoid the overhead of pinning pages repeatedly if buffers are reused. The registration cache is invalidated upon receipt of MMU notifier callbacks. SCIF windows are destroyed and the pages are unpinned only once all prior DMAs initiated using that window are drained. Users can request synchronous DMA operations as well as tail byte ordering if required. CPU copies are always performed synchronously. Reviewed-by:
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Sudeep Dutt authored
This patch implements the SCIF mmap/munmap interface. A similar capability is provided to kernel clients via the scif_get_pages()/scif_put_pages() APIs. The SCIF mmap interface queries to check if a window is valid and then remaps the local virtual address to the remote physical pages. These mappings are subsequently destroyed upon receipt of the VMA close operation or scif_get_pages(). This functionality allows SCIF users to directly access remote memory without any driver interaction once the mappings are created thereby providing bare-metal PCIe latency. These mappings are zapped to avoid RMA accesses from user space, if a Coprocessor is reset. Reviewed-by:
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Sudeep Dutt authored
This patch adds the implementation for operations performed on the list of SCIF windows. Examples of such operations includes adding the windows to the list of registered (or cached) windows, querying the list of self or remote windows and unregistering windows. The query operation is used by SCIF APIs which initiate DMAs, CPU copies or fences to ensure that a window remains valid during a transfer. Reviewed-by:
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Sudeep Dutt authored
This patch implements the SCIF APIs required to pin and unpin pages. SCIF registration locks down the pages. It then sends a remote window allocation request to the peer. Once the peer has allocated memory, the local SCIF endpoint copies the pinned page information to the peer and notifies the peer once the copy has complete. The peer upon receipt of the registration notification adds the new remote window to its list. At this point the window page information is available on both self and remote nodes so that they can start performing SCIF DMAs, CPU copies and fences. The unregistration API tears down the registration at both self and remote nodes. Reviewed-by:
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Sudeep Dutt authored
This patch adds the internal data structures required to perform SCIF RMAs. The data structures required to maintain per SCIF endpoint, RMA information are contained in scif_endpt_rma_info. scif_pinned_pages describes a set of SCIF pinned pages maintained locally. The scif_window is a data structure which contains all the fields required to describe a SCIF registered window on self and remote nodes. It contains an offset which is used as a key to perform SCIF DMAs and CPU copies between self and remote registered windows. Reviewed-by:
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Sudeep Dutt authored
This patch updates the SCIF header file and IOCTL interface with the changes required to support RMAs. APIs added include the ability to pin pages and register those pages with SCIF. SCIF kernel clients can also add references to remote registered pages and access them via the CPU. The user space IOCTL interface has been updated to enable SCIF registration, RDMA/CPU copies and fence APIs for RDMA synchronization. Reviewed-by:
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Ashutosh Dixit authored
This patch updates the MIC host daemon to work with corresponding changes in COSM. Other MIC daemon fixes, cleanups and enhancements as are also rolled into this patch. Changes to MIC sysfs ABI which go into effect with this patch are also documented. Reviewed-by:
Dasaratharaman Chandramouli <dasaratharaman.chandramouli@intel.com> Signed-off-by:
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Ashutosh Dixit authored
Since card side COSM functionality, to trigger MIC device shutdowns and communicate shutdown status to the host, is now moved into a separate COSM client driver, this patch removes this functionality from the base MIC card driver. The mic_bus driver is also updated to use the device index provided by COSM rather than maintain its own device index. Reviewed-by:
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Ashutosh Dixit authored
Since COSM functionality is now moved into a separate COSM driver drivers, this patch removes this functionality from the base MIC host driver. The MIC host driver now implements cosm_hw_ops and registers a COSM device which allows the COSM driver to trigger boot/shutdown/reset of the MIC devices via the cosm_hw_ops. Reviewed-by:
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Ashutosh Dixit authored
The COSM client driver running on the MIC cards is implemented as a kernel mode SCIF client. It responds to a "shutdown" message from the host by triggering a card shutdown and also communicates the shutdown or reboot status back the host. It is also responsible for syncing the card time to that of the host. Because SCIF messaging cannot be used in a panic context, the COSM client driver also periodically sends a heartbeat SCIF message to the host thereby enabling the host to detect card crashes. Reviewed-by:
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Ashutosh Dixit authored
The COSM driver communicates with the MIC cards over SCIF. A SCIF "server" listens for incoming connections from "client" MIC cards as they boot. After the connection is accepted a separate work item is scheduled for each MIC card. This work item normally stays blocked in scif_poll but wakes up to process messages from the card. The SCIF connection between the host and card COSM components is used to (a) send the command to shut down the card (b) receive shutdown status back from the card upon completion of shutdown (c) receive periodic heartbeat messages to detect card crashes (d) send host time to the card to enable the card to sync its time to the host. Reviewed-by:
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Ashutosh Dixit authored
The COSM driver allows boot, shutdown and reset of Intel MIC devices via sysfs. This functionality was previously present in the Intel MIC host driver but has now been taken out into a separate driver so that it can be shared between multiple generations of Intel MIC products. The sysfs kernel ABI used by the COSM driver is the same as that defined originally for the MIC host driver in Documentation/ABI/testing/sysfs-class-mic.txt. The COSM driver also contains support for dumping the MIC card log_buf and doing a "force reset" for the card via debugfs. The OSPM support present in the MIC host driver has now largely been moved to user space and only a small required OSPM functionality is now present in the driver. Reviewed-by:
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Ashutosh Dixit authored
The MIC COSM bus allows the co-processor state management (COSM) functionality to be shared between multiple generations of Intel MIC products. The COSM driver registers itself on the COSM bus. The base PCIe drivers implement the bus ops and register COSM devices on the bus, resulting in the COSM driver being probed with the COSM devices. COSM bus ops, e.g. start, stop, ready, reset, therefore abstract out common functionality from its specific implementation for individual generations of MIC products. Reviewed-by:
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