- 15 Aug, 2018 8 commits
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Stephen Boyd authored
Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next * clk-actions-s700: : - Actions Semi Owl series S700 SoC clk driver clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency * clk-exynos-unused: : - Remove an unused variable from Exynos4412 ISP driver clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable * clk-qcom-dispcc-845: : - Qualcomm SDM845 display clock controller clk: qcom: Add display clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Display clock bindings clk: qcom: Move frequency table macro to common file * clk-scmi-round: : - Fix a thinko bug in SCMI clk division logic clk: scmi: Fix the rounding of clock rate * clk-cs2000-spdx: clk: cs2000-cp: convert to SPDX identifiers
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Stephen Boyd authored
Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next * clk-imx6-ocram: : - i.MX6SX ocram_s clk support clk: imx: add ocram_s clock for i.mx6sx * clk-missing-put: : - Add missing of_node_put()s in some i.MX clk drivers clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() * clk-tegra-sdmmc-jitter: : - Tegra SDMMC clk jitter improvements with high speed signaling modes clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() * clk-allwinner: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs * clk-uniphier: : - Uniphier NAND, USB3 PHY, and SPI clk support clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock
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Stephen Boyd authored
Merge branches 'clk-qcom-rpmh', 'clk-qcom-spdx', 'clk-con-id-leak', 'clk-fixed-factor-populated' and 'clk-mvebu-periph-parent' into clk-next * clk-qcom-rpmh: : - Qualcomm RPMh clk driver clk: qcom: clk-rpmh: Add QCOM RPMh clock driver * clk-qcom-spdx: : - SPDX tagging for qcom clk: qcom: Update SPDX headers for common files * clk-con-id-leak: : - Stop leaking con ids in __clk_put() clk: core: Potentially free connection id * clk-fixed-factor-populated: : - Fix a corner case in fixed factor clk probing where node is in DT but : parent clk is registered much later clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failure * clk-mvebu-periph-parent: : - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value clk: mvebu: armada-37xx-periph: Remove unused var num_parents clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
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Stephen Boyd authored
Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next * clk-mvebu-spdx: clk: mvebu: armada-37xx-periph: switch to SPDX license identifier * clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL * clk-imx7d-mu: : - i.MX7D mailbox clk support clk: imx7d: add IMX7D_MU_ROOT_CLK * clk-imx-init-array-cleanup: : - i.MX clk init arrays removed in place of CLK_IS_CRITICAL clk: imx6sx: remove clks_init_on array clk: imx6sl: remove clks_init_on array clk: imx6q: remove clks_init_on array * clk-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
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Stephen Boyd authored
Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next * clk-imx-critical: : - Convert to CLK_IS_CRITICAL for i.MX51/53 driver clk: imx51-imx53: Include sizes.h to silence compile errors clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL * clk-tegra-bpmp: : - Fix Tegra BPMP driver oops when some xlating a NULL clk clk: tegra: bpmp: Don't crash when a clock fails to register * clk-tegra-124: : - Proper default configuration for vic03 and vde clks on Tegra124 clk: tegra: Make vde a child of pll_c3 clk: tegra: Make vic03 a child of pll_c3 * clk-tegra-critical: : - Mark Tegra memory controller clks as critical clk: tegra: Mark Memory Controller clock as critical * clk-tegra-emc-oob: : - Fix array bounds clamp in Tegra's emc determine_rate() op clk: tegra: emc: Avoid out-of-bounds bug
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Stephen Boyd authored
Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next * clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs
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Stephen Boyd authored
Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next * clk-imx6-video-parent: : - Fix i.MX6QDL video clk parent clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL * clk-qcom-sdm845-criticals: : - critical clk markings for qcom SDM845 clk: qcom: Enable clocks which needs to be always on for SDM845 * clk-renesas: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock * clk-stratix10-fixes: : - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents clk: socfpga: stratix10: fix the sdmmc_free_clk mux clk: socfpga: stratix10: fix the parents of mpu_free_clk * clk-atmel-i2s: : - Atmel at91 I2S audio clk support clk: at91: add I2S clock mux driver dt-bindings: clk: at91: add an I2S mux clock
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Stephen Boyd authored
Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', 'clk-core-duty-cycle', 'clk-si-prepare' and 'clk-imx-gpio-gates' into clk-next * clk-qcom-set-rate-gate: clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks * clk-core-set-rate-gate: clk: fix CLK_SET_RATE_GATE with clock rate protection * clk-core-duty-cycle: clk: add duty cycle support * clk-si-prepare: : - SI544/SI514 clk on/off support clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations * clk-imx-gpio-gates: : - i.MX6UL GPIO clock gates in CCM CCGR clk: imx6ul: remove clks_init_on array clk: imx6ul: add GPIO clock gates dt-bindings: clock: imx6ul: Do not change the clock definition order
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- 08 Aug, 2018 1 commit
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Stephen Boyd authored
Merge tag 'v4.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull one final rockchip update from Heiko Stuebner: pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core. * tag 'v4.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
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- 06 Aug, 2018 1 commit
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Levin Du authored
PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave from power on and the VDD_LOG is about 0.9V. When the kernel boots normally into the system, the PWM2 keeps outputing PWM signal. But the kernel hangs randomly after "Starting kernel ..." line on that board. When it happens, PWM2 outputs high level which causes VDD_LOG drops to 0.4V below the normal operating voltage. By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array, PWM clock is ensured to be prepared at startup and the PWM2 output is normal. After repeated tests, the early boot hang is gone. This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards. Signed-off-by:
Levin Du <djw@t-chip.com.cn> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- 02 Aug, 2018 2 commits
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Amit Daniel Kachhap authored
This fix rounds the clock rate properly by using quotient and not remainder in the calculation. This issue was found while testing HDMI in the Juno platform. Fixes: 6d6a1d82 ("clk: add support for clocks provided by SCMI") Acked-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by:
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- 01 Aug, 2018 1 commit
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Taniya Das authored
Add support for the display clock controller found on SDM845 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by:
Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere] Signed-off-by:
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- 27 Jul, 2018 1 commit
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Anders Roxell authored
When building armada-37xx-periph, num_parents isn't used in function clk_pm_cpu_get_parent: drivers/clk/mvebu/armada-37xx-periph.c: In function ‘clk_pm_cpu_get_parent’: drivers/clk/mvebu/armada-37xx-periph.c:419:6: warning: unused variable ‘num_parents’ [-Wunused-variable] int num_parents = clk_hw_get_num_parents(hw); ^~~~~~~~~~~ Remove the declaration of num_parents to dispose the warning. Fixes: 616bf80d ("clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent") Signed-off-by:Anders Roxell <anders.roxell@linaro.org> Signed-off-by:
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- 26 Jul, 2018 1 commit
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Krzysztof Kozlowski authored
Remove unused 'mout_user_aclk400_mcuisp_p4x12' variable to fix GCC warning: drivers/clk/samsung/clk-exynos4412-isp.c:40:27: warning: 'mout_user_aclk400_mcuisp_p4x12' defined but not used [-Wunused-const-variable=] Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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- 25 Jul, 2018 18 commits
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Saravanan Sekar authored
Add Actions Semi S700 SoC clock support Signed-off-by:
Parthiban Nallathambi <pn@denx.de> Signed-off-by:
Saravanan Sekar <sravanhome@gmail.com> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Saravanan Sekar authored
Add clock bindings constants for action S700 Maintain common clock dt-bindings for Actions Semi SoC's S700 and S900. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Saravanan Sekar authored
Add REGMAP_MMIO as dependency to avoid undefined reference to regmap symbols. Fixes: d85d2005 ("clk: actions: Add S900 SoC clock support") Signed-off-by:
Andreas Färber <afaerber@suse.de> Reviewed-by:
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Kunihiko Hayashi authored
Add clock control for SPI controller on UniPhier SoCs. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
Add USB3 PHY clocks where missing. Use fixed-factor clocks for those without gating. For clarification, prefix clock names with 'ss' or 'hs'. Signed-off-by:
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Masahiro Yamada authored
The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by:
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes for 4.19 from Maxime Ripard: Our usual bunch of clock patches, this time to enable the A64 display engine clocks controller mostly. * tag 'sunxi-clk-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs
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Peter De-Schrijver authored
These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by:
Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
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Peter De-Schrijver authored
Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
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Peter De Schrijver authored
Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by:
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Aapo Vienamo authored
Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by:
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Nicholas Mc Guire authored
of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Fixes: 4a5f720b ("clk: imx: add clock driver for imx6sll") Signed-off-by:
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Nicholas Mc Guire authored
of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by:
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Anson Huang authored
i.MX6SX has a 16KB always-on ocram bank called ocram_s, and its clock gate in CCM CCGR1 CG14 needs to be enabled before access, add it to clock tree. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Gregory CLEMENT authored
The return value of the get_parent operation is a u8, whereas a -EINVAL was returned. This wrong value was return if the value was bigger that the number of parent but this case was already handled by the core. So we can just remove this chunk of code to fix the issue. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Fixes: 9818a7a4 ("clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS") Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
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Rajan Vaja authored
Fixed factor clock has two initializations at of_clk_init() time and during platform driver probe. Before of_clk_init() call, node is marked as populated and so its probe never gets called. During of_clk_init() fixed factor clock registration may fail if any of its parent clock is not registered. In this case, it doesn't get chance to retry registration from probe. Clear OF_POPULATED flag if fixed factor clock registration fails so that clock registration is attempted again from probe. Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by:
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Mikko Perttunen authored
Patch "clk: core: Copy connection id" made it so that the connector id 'con_id' is kstrdup_const()ed to cater to drivers that pass non-constant connection ids. The patch added the corresponding kfree_const to __clk_free_clk(), but struct clk's can be freed also via __clk_put(). Add the kfree_const call to __clk_put() and add comments to both functions to remind that the logic in them should be kept in sync. Fixes: 253160a8 ("clk: core: Copy connection id") Signed-off-by:
Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
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Taniya Das authored
SPDX headers updated for common/branch/pll/regmap files. Signed-off-by:
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- 16 Jul, 2018 1 commit
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Taniya Das authored
Add the RPMh clock driver to control the RPMh managed clock resources on some of the Qualcomm Technologies, Inc. SoCs. Signed-off-by:
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- 11 Jul, 2018 1 commit
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Stephen Boyd authored
Merge tag 'v4.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Support for Rockchip's PX30 SoC including its new half-divider clock type that is doing freq_out = 2*freq_in / (2*div + 3). As well as a register-bit fix for the rk3399 i2sout clock. * tag 'v4.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
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- 09 Jul, 2018 5 commits
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Oleksij Rempel authored
This clock is needed for iMX mailbox driver Signed-off-by:
Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by:
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https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull first round of updates for meson clocks from Jerome Brunet: - Remove legacy register access (finish moving to syscon) - Clean up configuration flags - Add axg PCIe clocks - Add GEN CLK on gxbb, gxl and axg - Remove clk_audio_divider driver - Add axg audio clock controller * tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: add duty cycle support clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
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Gregory CLEMENT authored
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by:
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Jerome Brunet authored
GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by:Jerome Brunet <jbrunet@baylibre.com>
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Jerome Brunet authored
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition Fixes: 738f66d3 ("clk: gxbb: add AmLogic GXBB clk controller driver") Acked-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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