1. 29 Nov, 2017 1 commit
    • Vaibhav Jain's avatar
      powerpc: Avoid signed to unsigned conversion in set_thread_tidr() · aca7573f
      Vaibhav Jain authored
      There is an unsafe signed to unsigned conversion in set_thread_tidr()
      that may cause an error value to be assigned to SPRN_TIDR register and
      used as thread-id.
      
      The issue happens as assign_thread_tidr() returns an int and
      thread.tidr is an unsigned-long. So a negative error code returned
      from assign_thread_tidr() will fail the error check and gets assigned
      as tidr as a large positive value.
      
      To fix this the patch assigns the return value of assign_thread_tidr()
      to a temporary int and assigns it to thread.tidr iff its '> 0'.
      
      The patch shouldn't impact the calling convention of set_thread_tidr()
      i.e all -ve return-values are error codes and a return value of '0'
      indicates success.
      
      Fixes: ec233ede("powerpc: Add support for setting SPRN_TIDR")
      Signed-off-by: default avatarVaibhav Jain <vaibhav@linux.vnet.ibm.com>
      Reviewed-by: Christophe Lombard clombard@linux.vnet.ibm.com
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      aca7573f
  2. 24 Nov, 2017 1 commit
  3. 23 Nov, 2017 2 commits
  4. 22 Nov, 2017 5 commits
  5. 21 Nov, 2017 1 commit
  6. 20 Nov, 2017 1 commit
  7. 15 Nov, 2017 1 commit
    • Michael Ellerman's avatar
      powerpc/64s: Fix Power9 DD2.0 workarounds by adding DD2.1 feature · 3ffa9d9e
      Michael Ellerman authored
      Recently we added a CPU feature for Power9 DD2.0, to capture the fact
      that some workarounds are required only on Power9 DD1 and DD2.0 but
      not DD2.1 or later.
      
      Then in commit 9d2f510a ("powerpc/64s/idle: avoid POWER9 DD1 and
      DD2.0 ERAT workaround on DD2.1") and commit e3646330
      "powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 PMU workaround on
      DD2.1") we changed CPU_FTR_SECTIONs to check for DD1 or DD20, eg:
      
        BEGIN_FTR_SECTION
                PPC_INVALIDATE_ERAT
        END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1 | CPU_FTR_POWER9_DD20)
      
      Unfortunately although this reads as "if set DD1 or DD2.0", the or is
      a bitwise or and actually generates a mask of both bits. The code that
      does the feature patching then checks that the value of the CPU
      features masked with that mask are equal to the mask.
      
      So the end result is we're checking for DD1 and DD20 being set, which
      never happens. Yes the API is terrible.
      
      Removing the ERAT workaround on DD2.0 results in random SEGVs, the
      system tends to boot, but things randomly die including sometimes
      dhclient, udev etc.
      
      To fix the problem and hopefully avoid it in future, we remove the
      DD2.0 CPU feature and instead add a DD2.1 (or later) feature. This
      allows us to easily express that the workarounds are required if DD2.1
      is not set.
      
      At some point we will drop the DD1 workarounds entirely and some of
      this can be cleaned up.
      
      Fixes: 9d2f510a ("powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 ERAT workaround on DD2.1")
      Fixes: e3646330 ("powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 PMU workaround on DD2.1")
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      3ffa9d9e
  8. 14 Nov, 2017 1 commit
    • Michael Ellerman's avatar
      powerpc/64s: Fix masking of SRR1 bits on instruction fault · 475b581f
      Michael Ellerman authored
      On 64-bit Book3s, when we take an instruction fault the reason for the
      fault may be reported in SRR1. For data faults the reason is reported
      in DSISR (Data Storage Instruction Status Register).
      
      The reasons reported in each do not necessarily correspond, so we mask
      the SRR1 bits before copying them to the DSISR, which is then used by
      the page fault code.
      
      Prior to commit b4c001dc ("powerpc/mm: Use symbolic constants for
      filtering SRR1 bits on ISIs") we used a hard-coded mask of 0x58200000,
      which corresponds to:
      
        DSISR_NOHPTE		0x40000000 /* no translation found */
        DSISR_NOEXEC_OR_G	0x10000000 /* exec of no-exec or guarded */
        DSISR_PROTFAULT	0x08000000 /* protection fault */
        DSISR_KEYFAULT	0x00200000 /* Storage Key fault */
      
      That commit added a #define for the mask, DSISR_SRR1_MATCH_64S, but
      incorrectly used a different similarly named DSISR_BAD_FAULT_64S.
      
      This had the effect of changing the mask to 0xa43a0000, which omits
      everything but DSISR_KEYFAULT.
      
      Luckily this had no visible effect, because in practice we hardly use
      the DSISR bits. The lack of DSISR_NOHPTE means a TLB flush
      optimisation was missed in the native HPTE code, and DSISR_NOEXEC_OR_G
      and DSISR_PROTFAULT are both only used to trigger rare warnings.
      
      So we got lucky, but let's fix it. The new value only has bits between
      17 and 30 set, so we can continue to use andis.
      
      Fixes: b4c001dc ("powerpc/mm: Use symbolic constants for filtering SRR1 bits on ISIs")
      Cc: stable@vger.kernel.org # v4.14+
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      475b581f
  9. 13 Nov, 2017 7 commits
  10. 12 Nov, 2017 13 commits
  11. 11 Nov, 2017 7 commits